Shift resistor circuit and method of operating the same

• US 20050264513A1
• Filed: 05/27/2005
• Published: 12/01/2005
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lim, Kyoung Moon
• Granted Patent: US 7,561,655 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shit resistor circuit and a method of operating the same are disclosed. The shift resistor circuit includes an OR-gate unit for receiving a start pulse or an output of a previous stage and a feedback signal; a level shift unit for level-shifting a swing voltage of a clock signal in response to an output signal of the OR-gate unit; and a buffer for transferring an output of the level shift unit to a next stage as an input signal.

Claims

1. A shift resistor circuit, comprising:

an OR-gate unit for receiving a start pulse or an output of a previous stage and a feedback signal;

a level shift unit for level-shifting a swing voltage of a clock signal in response to an output signal of the OR-gate unit; and

a buffer for transferring an output of the level shift unit to a next stage as an input signal.

2. The shift resistor circuit according to claim 1, wherein the clock signal is one of two-phase clock signals and the two-phase clock signals are complementary to each other.

3. The shift resistor circuit according to claim 2, wherein the two-phase clock signals have a swing voltage lower than 10V and are inputted from an external circuit.

4. The shift resistor circuit according to claim 1, wherein the OR-gate unit includes an NOR-gate circuit and an inverter circuit serially connected to the NOR-gate circuit.

5. The shift resistor circuit according to claim 4, wherein the NOR-gate circuit includes two PMOS transistors (T1, T2) connected in serial and two NMOS transistors (T3, T4) connected in parallel which are connected to the two PMOS transistors in serial, and the inverter circuit includes an NMOS transistor (T5) and a PMOS transistor (T6)

6. The sift resistor circuit according to claim 1, wherein the level shift unit includes a plurality of NMOS transistors and a plurality of PMOS transistors, and a predetermined bias voltage is additionally applied to the level shift unit.

7. The shift resistor circuit according to claim 1, wherein the feedback signal is a signal outputted from a first inverter in the buffer after the clock signal is inputted to the level shift unit.

8. The shift resistor circuit according to claim 5, wherein the output signal of the OR-gate unit is generated by inputting the feedback signal to the T1 and T4, inputting the start pulse to T2 and T3, and passing the outputs through the T5 and T6.

9. The sift resistor circuit according to claim 1, wherein the level shift unit operates only when the OR-gate unit generates a high state.

10. The shift resistor circuit according to claim 1, wherein the buffer includes a plurality of inverter circuits connected in a cascade form and an output of a first inverter circuit is feed-backed to a transistor of the OR-gate unit.

11. A method of operating a shift resistor circuit, comprising:

inputting a start pulse or an output of a previous stage and a feedback signal to an OR-gate unit;

defining an operating period by an output signal of the OR-gate unit and level-shifting a swing voltage of a clock signal by a level shift unit; and

transferring an output of the level shift unit to a next state using a buffer.

12. The method according to claim 11, wherein the clock signal is one of two-phase clock signals and the two-phase clock signals are complementary to each other.

13. The method according to claim 12, wherein the two-phase clock signals have a swing voltage lower than 10V and are inputted from an external circuit.

14. The method according to claim 11, wherein the feedback signal is a signal outputted from a first inverter in the buffer after the clock signal is inputted to the level shift unit.

15. The method according to claim 11, wherein the level shift unit operates only when the OR-gate unit generates a high state.

16. A display device, comprising:

an image display unit for displaying images and a control chip for generating a clock signal; and

a shift register circuit electrically connected to the image display unit and the control chip, the shift register circuit including a level shift unit for level-shifting a swing voltage of the clock signal.

17. The display device according to claim 16, the shift register circuit further comprising:

an OR-gate unit for receiving a start pulse or an output of a previous stage and a feedback signal; and

a buffer for transferring an output of the level shift unit to a next stage as an input signal.

18. The display device according to claim 17, wherein the level shift unit level-shifts the swing voltage of the clock signal in response to an output signal of the OR-gate unit.

19. The display device according to claim 17, wherein the feedback signal is a signal outputted from the buffer.

20. The display device according to claim 17, wherein the display device is a liquid crystal display.