×

Shift register

  • US 20050264514A1
  • Filed: 05/31/2005
  • Published: 12/01/2005
  • Est. Priority Date: 05/31/2004
  • Status: Active Grant
First Claim
Patent Images

1. A shift register having a plurality of stages, comprising:

  • first, second, and third driving voltage supply lines;

    at least two clock signal supply lines;

    an output buffer having an output pull-up transistor and first and second output pull-down transistors;

    a first controller having an input connected to a start signal supply line and an output connected to a first node; and

    a second controller having an input connected to the first and second voltage supply lines and an output connected to gates of the first and second output pull-down transistors.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×