Shift register

• US 20050264514A1
• Filed: 05/31/2005
• Published: 12/01/2005
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Binn, Yoon, Soo Young
• Granted Patent: US 7,477,226 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-down transistors substantially mitigates gate stress, and substantially enables the shift register to be fabricated with amorphous silicon.

Claims

1. A shift register having a plurality of stages, comprising:

first, second, and third driving voltage supply lines;

at least two clock signal supply lines;

an output buffer having an output pull-up transistor and first and second output pull-down transistors;

a first controller having an input connected to a start signal supply line and an output connected to a first node; and

a second controller having an input connected to the first and second voltage supply lines and an output connected to gates of the first and second output pull-down transistors.

2. The stage according to claim 1, wherein the first controller includes:

a charge transistor having a gate connected to the start signal supply line and an output connected to the first node; and

a plurality of discharge transistors connected to the first node and the third driving voltage supply line.

3. The stage according to claim 2, wherein the first node is connected to a gate of the pull-up output transistor.

4. The stage according to claim 2, wherein the plurality of discharge transistors includes:

a first discharge transistor having a gate connected to an odd frame output node; and

a second discharge transistor having a gate connected to an even frame output node.

5. The stage according to claim 4, wherein the second controller includes an odd frame voltage control transistor having a gate connected to the first driving voltage supply line and an output connected to the odd frame output node.

6. The stage according to claim 4, wherein the second controller includes an even frame voltage control transistor having a gate connected to the even frame output node.

7. The stage according to claim 4, further including a third discharge control transistor having a gate connected to an output of a later stage.

8. The stage according to claim 4, wherein the odd frame output node is connected to a gate of the first output pull-down transistor.

9. The stage according to claim 4, wherein the even frame output node is connected to a gate of the second output pull-down transistor.

10. The stage of claim 1, wherein the output pull-up transistor and the first and second output pull-down transistors include amorphous silicon.

11. A shift register having a plurality of stages, comprising:

an output buffer having a first transistor and an even and odd transistor, the even and odd transistors having the same polarity;

a first controller for controlling an output state of the output buffer; and

a second controller for switching an output control between the even and odd transistor.

13. The stage according to claim 11, further comprising a start signal supply line connected to the first controller.

14. The stage according to claim 11, wherein the first controller is connected to an output of a subsequent stage.

15. The stage according to claim 11, further comprising a clock signal supply line connected to the output buffer.

16. The stage according to claim 11, wherein the first transistor and the even and odd transistors include amorphous silicon.

12. The stage according to claim 12, further comprising:

first and second voltage supply lines connected to the second controller.