Method of implementing an accelerated graphics port for a multiple memory controller computer system
First Claim
1. A method of manufacturing a multiple memory controller computer comprising:
- providing at least two memory controllers for controlling a main memory; and
connecting a first of the at least two memory controllers to an I/O processor;
wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor, and wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers.
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Abstract
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.
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Citations
20 Claims
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1. A method of manufacturing a multiple memory controller computer comprising:
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providing at least two memory controllers for controlling a main memory; and
connecting a first of the at least two memory controllers to an I/O processor;
wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor, and wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multiple memory controller computer comprising:
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at least two memory controllers for controlling a main memory; and
an I/O processor connected to a first of the at least two memory controllers;
wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor; and
wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A multiple memory controller computer comprising:
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means for providing at least two memory controllers for controlling a main memory; and
means for connecting a first of the at least two memory controllers to an I/O processor;
wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor, and wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers. - View Dependent Claims (18, 19, 20)
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Specification