Method of implementing an accelerated graphics port for a multiple memory controller computer system

• US 20050264575A1
• Filed: 07/27/2005
• Published: 12/01/2005
• Est. Priority Date: 12/30/1997
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph
• Granted Patent: US 7,777,752 B2
• Time in Patent Office: Days
• US Class Current: 345/532
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.

Claims

1. A method of manufacturing a multiple memory controller computer comprising:

providing at least two memory controllers for controlling a main memory; and

connecting a first of the at least two memory controllers to an I/O processor;

wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor, and wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers.

2. The method of claim 1, further comprising providing in the main memory an address remapping table having at least one page table entry (PTE) which provides information for a translation of a virtual address to a physical address, wherein the virtual address includes a first portion and a second portion, the first portion corresponding to a PTE in the address remapping table and wherein the second portion and information provided by the PTE are combined to provide the physical address.

3. The method of claim 2, further comprising allocating a virtual page number field to the first portion.

4. The method of claim 2, further comprising allocating an offset field to the second portion.

5. The method of claim 1, further comprising manufacturing the at least two memory controllers and the main memory on a single semiconductor chip.

6. The method of claim 1 wherein the first of the at least two memory controllers is connected to the I/O processor via a point-to-point connection, and wherein the point-to-point connection is configured to transfer addresses and data associated with I/O processor transactions.

7. The method of claim 6 wherein the first of the at least two memory controllers receives data in a range register defining the amount of memory that is preferentially used over other addresses for storage of data for I/O processor transactions via the point-to-point connection.

8. A multiple memory controller computer comprising:

at least two memory controllers for controlling a main memory; and

an I/O processor connected to a first of the at least two memory controllers;

wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor; and

wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers.

9. The computer of claim 8 wherein the first of the at least two memory controllers is connected to the I/O processor via a point-to-point connection, and wherein the point-to-point connection is configured to transfer addresses and data associated with I/O processor transactions.

10. The computer of claim 8 wherein the first of the at least two memory controllers is configured to receive data during boot up of a computer system.

11. The computer of claim 8 wherein the first of the at least two memory controllers receives data in a base address register defining the starting point of memory preferentially used over other addresses for storage of I/O data for I/O processor transactions.

12. The computer of claim 8 wherein the first of the at least two memory controllers receives data setting a boundary address register defining the lowest address of an address remapping table.

13. The computer of claim 8 wherein the first of the at least two memory controllers receives data in a range register defining the amount of memory that is preferentially used over other addresses for storage of data for I/O processor transactions via the point-to-point connection.

14. The computer of claim 8 wherein the first of the at least two memory controllers receives data from an initialization BIOS.

15. The computer of claim 8 wherein the first of the at least two memory controllers receives data from the operating system API.

16. The computer of claim 8 wherein the at least two memory controllers and the main memory are manufactured on a single semiconductor chip.

17. A multiple memory controller computer comprising:

means for providing at least two memory controllers for controlling a main memory; and

means for connecting a first of the at least two memory controllers to an I/O processor;

wherein a second of the at least two memory controllers handles requests that are not meant for the I/O processor, and wherein the first of the at least two memory controllers is configured to reroute requests that are not meant for the I/O processor to the second of the at least two memory controllers.

18. The computer of claim 17 wherein the at least two memory controllers and the main memory are manufactured on a single semiconductor chip.

19. The computer of claim 17 wherein the first of the at least two memory controllers is connected to the I/O processor via a point-to-point connection, and wherein the point-to-point connection is configured to transfer addresses and data associated with I/O processor transactions.

20. The computer of claim 19 wherein the first of the at least two memory controllers receives data in a range register defining the amount of memory that is preferentially used over other addresses for storage of data for I/O processor transactions via the point-to-point connection.