Chip to chip interface

• US 20050265062A1
• Filed: 05/26/2004
• Published: 12/01/2005
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Walker, Robert
• Granted Patent: US 7,129,753 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A chip to chip interface comprising a signal line configured to receive a first signal and a receiver. The receiver is configured to provide a first output signal that corresponds to a first bit in response to a clock signal, wherein the receiver is configured to toggle the first bit based on the first output signal and in response to the first signal.

Claims

1. A chip to chip interface comprising:

a signal line configured to receive a first signal; and

a receiver configured to provide a first output signal that corresponds to a first bit in response to a clock signal, wherein the receiver is configured to toggle the first bit based on the first output signal and in response to the first signal.

2. The chip to chip interface of claim 1, wherein the receiver is configured to toggle the first bit in response to the first signal with the first output signal at the same logic level as the first bit.

3. The chip to chip interface of claim 1, wherein the first signal represents a change in data at one edge of the clock signal and the receiver is configured to provide the first output signal in response to the one edge of the clock signal, wherein the first output signal represents the data.

4. The chip to chip interface of claim 1, wherein the receiver comprises a flip-flop configured to toggle the first bit based on the first output signal and in response to the first signal.

5. The chip to chip interface of claim 4, wherein the receiver comprises:

an inverter configured to invert the first output signal and provide the inverted first output signal to the flip-flop.

6. The chip to chip interface of claim 1, wherein the receiver comprises an input latch configured to toggle the first bit based on the first output signal and in response to the first signal.

7. The chip to chip interface of claim 6, wherein the first output signal is provided to the input latch.

8. The chip to chip interface of claim 1, comprising:

a driver configured to provide the first signal in response to a change in data at one edge of the clock signal.

9. The chip to chip interface of claim 1, wherein the signal line is configured to receive a second signal and the receiver is configured to provide a second output signal that corresponds to a second bit in response to the clock signal, and to toggle the second bit based on the second output signal and in response to the second signal.

10. The chip to chip interface of claim 9, wherein the first signal is received in one portion of the clock signal and the second signal is received in another portion of the clock signal.

11. The chip to chip interface of claim 10, wherein the one portion is one half cycle of the clock signal and the second portion is another half cycle of the clock signal.

12. The chip to chip interface of claim 9, comprising:

a driver configured to provide the first signal in response to a change in first data at one edge of the clock signal and the second signal in response to a change in second data at another edge of the clock signal.

13. The chip to chip interface of claim 12, wherein the first output signal represents the first data and the second output signal represents the second data.

14. The chip to chip interface of claim 12, wherein the first data is positive edge data in a double data rate data stream and the second data is negative edge data in a double data rate data stream.

15. A chip to chip interface comprising:

a driver configured to provide a first signal in response to a change in first data at one edge of a clock signal; and

a receiver comprising;

a first stage configured to receive the first signal and provide a first bit; and

a second stage configured to receive the first bit and provide a first output signal that corresponds to the first bit in response to the clock signal, wherein the first stage is configured to toggle the first bit based on the first output signal and in response to the first signal.

16. The chip to chip interface of claim 15, wherein the first stage is configured to toggle the first bit in response to the first signal with the first output signal at the same logic level as the first bit.

17. The chip to chip interface of claim 15, wherein the second stage is configured to provide the first output signal that corresponds to the first bit in response to the one edge of the clock signal.

18. The chip to chip interface of claim 15, wherein the receiver comprises a flip-flop configured to toggle the first bit based on the first output signal and in response to the first signal.

19. The chip to chip interface of claim 15, wherein the receiver comprises an input latch configured to toggle the first bit based on the first output signal and in response to the first signal.

20. The chip to chip interface of claim 15, wherein the driver is configured to provide a second signal in response to a change in second data at another edge of the clock signal, the first stage is configured to receive the second signal and provide a second bit, and the second stage is configured to receive the second bit and provide a second output signal that corresponds to the second bit in response to the clock signal, wherein the first stage is configured to toggle the second bit based on the second output signal and in response to the second signal.

21. The chip to chip interface of claim 20, wherein the second stage is configured to provide the first output signal that corresponds to the first bit in response to the one edge of the clock signal and the second stage is configured to provide the second output signal that corresponds to the second bit in response to the other edge of the clock signal.

22. The chip to chip interface of claim 20, wherein the driver is configured to receive a double data rate data signal and provide a high voltage pulse as the first signal in response to a change in positive edge data and a low voltage pulse as the second signal in response to a change in negative edge data.

23. The chip to chip interface of claim 22, wherein the receiver comprises:

a first comparator configured to toggle the first bit; and

a second comparator configured to toggle the second bit, wherein the first comparator receives a first reference signal to compare to the high voltage pulse and the second comparator receives a second reference signal to compare to the low voltage pulse.

24. A chip to chip interface comprising:

a driver configured to provide a signal in response to a change in data at one edge of a clock signal; and

a receiver comprising;

a first flip-flop configured to respond to the signal and provide a first output signal; and

a second flip-flop configured to provide a second output signal that corresponds to the first output signal in response to the clock signal, wherein the first flip-flop is configured to change the first output signal based on the second output signal and in response to the signal.

25. The chip to chip interface of claim 24, wherein the first flip-flop is configured to change the first output signal in response to the signal with the second output signal at the same logic level as the first output signal and the second flip-flop is configured to provide the second output signal corresponding to the first output signal in response to the one edge of the clock signal.

26. A chip to chip interface comprising:

a driver configured to provide a signal in response to a change in data at one edge of a clock signal; and

a receiver comprising;

an input latch configured to respond to the signal and provide a first output signal; and

a flip-flop configured to provide a second output signal that corresponds to the first output signal in response to the clock signal, wherein the input latch changes the first output signal based on the second output signal and in response to the signal.

27. The chip to chip interface of claim 26, wherein the input latch is configured to change the first output signal in response to the signal with the second output signal at the same logic level as the first output signal and the flip-flop is configured to provide the second output signal corresponding to the first output signal in response to the one edge of the clock signal.

28. A chip to chip interface comprising:

means for receiving a first signal;

means for providing a first output signal that corresponds to a first bit in response to a clock signal; and

means for changing the first bit based on the first output signal and in response to the first signal.

29. The chip to chip interface of claim 28, wherein the means for changing comprises:

means for responding to the first signal to provide a first signal clock; and

means for toggling the first bit based on receiving the first signal clock while the first output signal is at the same logic level as the first bit.

30. The chip to chip interface of claim 28, wherein the first signal corresponds to a change in data at one edge of the clock signal and the means for providing comprises:

means for providing the first output signal in response to the one edge of the clock signal.

31. The chip to chip interface of claim 28, comprising:

means for providing the first signal in response to a change in data at one edge of the clock signal.

32. The chip to chip interface of claim 28, comprising:

means for receiving a second signal;

means for providing a second output signal that corresponds to a second bit in response to the clock signal; and

means for changing the second bit based on the second output signal and in response to the second signal.

33. The chip to chip interface of claim 32, comprising:

means for providing the first signal in response to a change in first data at one edge of the clock signal; and

means for providing the second signal in response to a change in second data at another edge of the clock signal.

34. A method for communicating data between chips comprising:

receiving a first signal;

providing a first output signal that corresponds to a first bit in response to a clock signal; and

changing the first bit based on the first output signal and in response to the first signal.

35. The method of claim 34, wherein changing the first bit comprises:

responding to the first signal to provide a first signal clock;

receiving the first signal clock while the first output signal is at the same logic level as the first bit; and

toggling the first bit.

36. The method of claim 34, comprising:

providing the first signal in response to a change in data at one edge of the clock signal, wherein providing the first output signal comprises providing the first output signal in response to the one edge of the clock signal.

37. The method of claim 34, comprising:

receiving a second signal;

providing a second output signal that corresponds to a second bit in response to the clock signal; and

changing the second bit based on the second output signal and in response to the second signal.

38. The method of claim 37, comprising:

providing the first signal in response to a change in first data at one edge of the clock signal; and

providing the second signal in response to a change in second data at another edge of the clock signal.