Semiconductor device fabricating method

• US 20050266631A1
• Filed: 04/05/2005
• Published: 12/01/2005
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Mori, Toshifumi, Kim, Young Suk
• Granted Patent: US 7,407,860 B2
• Time in Patent Office: Days
• US Class Current: 438/216
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30a. Then, impurities are implanted in the p-MOS region 30a and the n-MOS region 30b to form shallow junction regions 22a, 22b and deep junction regions 23a, 23b. The impurity in the shallow junction regions 22a, 22b is prevented from being diffused immediately below the gate insulation film 15 by the thermal processing in forming the SiGe film, the short channel effect is prevented, and the hole mobility of the channel region of the p-MOS transistor 14a. The operation speed of the p-MOS transistor 13a is balanced with that of the n-MOS transistor, whereby the operation speed of the complementary semiconductor device 10 can be increased. The semiconductor device fabricating method can increase and balance the operation speed of a p-transistor with that of an n-transistor.

Claims

1. A semiconductor device fabricating method for fabricating a semiconductor device including a p-transistor formed in a first region of a semiconductor substrate, and an n-transistor formed in a second region of the semiconductor substrate, comprising the steps of:

forming a first gate layer structure including a gate insulation film and a gate electrode in the first region and a second gate layer structure including a gate insulation film and a gate electrode in the second region;

forming a first sidewall insulation film on both side surfaces of the first gate layer structure;

forming a trench in the semiconductor substrate outer of the first sidewall insulation film with the surface of the semiconductor substrate in the first region with the first sidewall insulation film as a mask, the second region covered with an etching resistant film and;

forming a compressive stress applying portion in the trench;

removing the first sidewall insulation film in the first region;

forming a first junction region in the first region and the second region with the first gate layer structure and the second gate layer structure as a mask;

forming a second sidewall insulation film on both side surfaces of the first gate layer structure and a third sidewall insulation film on both side surfaces of the second gate layer structure; and

forming a second junction region in the first region and the second region with the first gate layer structure and the second sidewall insulation film and the second gate layer structure and the third sidewall insulation film as a mask.

2. A semiconductor device fabricating method according to claim 1, wherein

the step of forming the first sidewall insulation film includes the steps of:

forming sequentially a first insulation film and a second insulation film covering the surface of the semiconductor substrate and the first gate layer structure and the second gate layer structure; and

anisotropically etching the first insulation film and the second insulation film in the first region, and

in the step of forming the trench, the etching resistant film in the second region is the second insulation film covering the second region.

3. A semiconductor device fabricating method according to claim 1, wherein

in the step of forming the trench, the etching resistant film in the second region is a resist film covering the second region.

5. A semiconductor device fabricating method according to claim 1, wherein

after the step of forming the first junction region in the first region and the second region and before the step of forming the second sidewall insulation film and the third sidewall insulation film,

the method further comprises the steps of;

forming a fourth sidewall insulation film which is thinner than the second sidewall insulation film on both side surfaces of the first gate layer structure, and forming a fifth sidewall insulation film which is thinner than the third sidewall insulation film on both side surfaces of the second gate layer structure; and

forming a third junction region which is deeper than the first junction region and shallower than the second junction region, in the first region with the first gate layer structure and the fourth sidewall insulation film as a mask, and in the second region with the second gate layer structure and the fifth sidewall insulation film as a mask.

7. A semiconductor device fabricating method according to claim 1, wherein

the step of forming the trenche comprises:

anisotropically etching the semiconductor substrate outer of the first sidewall insulation film; and

isotropically etching the semiconductor substrate outer of the first sidewall insulation film.

9. A semiconductor device fabricating method according to claim 7, wherein

the isotropic etching is chemical dry etching using hydrogen chloride gas or chlorine gas.

11. A semiconductor device fabricating method according to claim 7, wherein

the trench is so set that the end of the trench is spaced from the end of the first gate layer structure by 5-80 nm.

13. A semiconductor device fabricating method according to claim 1, wherein

the step of forming a compressive stress applying portions comprises the step of epitaxially growing in the trenches a semiconductor material whose lattice constant is larger than that of a semiconductor forming the semiconductor substrate.

15. A semiconductor device fabricating method according to claim 1,

further comprising, after the step of forming the first gate layer structure and the second gate layer structure, the step of forming a cap layer on the fist gate layer structure, and

the step of forming the trench uses the cap layer as a mask for the first gate layer structure.

17. A semiconductor device fabricating method according to claim 15, wherein

in the step of forming the compressive stress applying portion, the cap layer is used as a mask for the first gate layer structure.

19. A semiconductor device fabricating method according to claim 1, wherein

the semiconductor substrate is a silicon substrate, and the compressive stress applying portion is formed of SiGe film or SiGeC film.

4. A semiconductor device fabricating method for fabricating a semiconductor device including a p-transistor formed in a first region of a semiconductor substrate, and an n-transistor formed in a second region of the semiconductor substrate, comprising the steps of:

forming a first gate layer structure including a gate insulation film and a gate electrode in the first region and a second gate layer structure including a gate insulation film and a gate electrode in the second region;

forming a first sidewall insulation film on both side surfaces of the first gate layer structure;

performing a first surface processing in which CF₄ gas and O₂ gas are electrolytically dissociated and applied, the second region covered with a resist film, to thereby deform the surface of the semiconductor substrate outer of the first sidewall insulation film in the first region to form a first deformed film thereon;

performing a second surface processing in which O₂ gas is electrolytically dissociated and applied to thereby remove the resist film in the second region, and to further deform the first deformed film to form a second deformed film and to oxide the surface of the semiconductor substrate exposed in the second region to form an oxide film thereon;

forming a trench in the semiconductor substrate outer of the first sidewall insulation film with the surface of the semiconductor substrate in the first region with the first gate layer structure and the first sidewall insulation film in the first region and the second gate layer structure and the oxide film in the second region as a mask;

forming a compressive stress applying portion in the trench;

removing the first sidewall insulation film in the first region;

forming a first junction region in the first region and the second region with the first gate layer structure and the second gate layer structure as a mask;

forming a second sidewall insulation film on both side surfaces of the first gate layer structure and a third sidewall insulation film on both side surfaces of the second gate layer structure; and

forming a second junction region in the first region and the second region with the first gate layer structure and the second sidewall insulation film and the second gate layer structure and the third sidewall insulation film as a mask.

6. A semiconductor device fabricating method according to claim 4, wherein

after the step of forming the first junction region in the first region and the second region and before the step of forming the second sidewall insulation film and the third sidewall insulation film,

the method further comprises the steps of;

forming a fourth sidewall insulation film which is thinner than the second sidewall insulation film on both side surfaces of the first gate layer structure, and

forming a fifth sidewall insulation film which is thinner than the third sidewall insulation film on both side surfaces of the second gate layer structure; and

forming a third junction region which is deeper than the first junction region and shallower than the second junction region, in the first region with the first gate layer structure and the fourth sidewall insulation film as a mask, and in the second region with the second gate layer structure and the fifth sidewall insulation film as a mask.

8. A semiconductor device fabricating method according to claim 4, wherein

the step of forming the trenche comprises:

anisotropically etching the semiconductor substrate outer of the first sidewall insulation film; and

isotropically etching the semiconductor substrate outer of the first sidewall insulation film.

10. A semiconductor device fabricating method according to claim 8, wherein

the isotropic etching is chemical dry etching using hydrogen chloride gas or chlorine gas.

12. A semiconductor device fabricating method according to claim 8, wherein

the trench is so set that the end of the trench is spaced from the end of the first gate layer structure by 5-80 nm.

14. A semiconductor device fabricating method according to claim 4, wherein

the step of forming a compressive stress applying portions comprises the step of epitaxially growing in the trenches a semiconductor material whose lattice constant is larger than that of a semiconductor forming the semiconductor substrate.

16. A semiconductor device fabricating method according to claim 4,

further comprising, after the step of forming the first gate layer structure and the second gate layer structure, the step of forming a cap layer on the fist gate layer structure, and

the step of forming the trench uses the cap layer as a mask for the first gate layer structure.

18. A semiconductor device fabricating method according to claim 16, wherein

in the step of forming the compressive stress applying portion, the cap layer is used as a mask for the first gate layer structure.

20. A semiconductor device fabricating method according to claim 4, wherein

the semiconductor substrate is a silicon substrate, and the compressive stress applying portion is formed of SiGe film or SiGeC film.