Semiconductor device and a method of fabricating the same

• US 20050266642A1
• Filed: 08/02/2005
• Published: 12/01/2005
• Est. Priority Date: 09/29/1998
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Saito, Hiroaki, Onda, Masahito, Kubo, Hirotoshi, Kitagawa, Masanao, Kuwako, Eiichiroh
• Granted Patent: US 7,521,306 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 which is exposed through the recess, the side wall insulator 28, and the insulating film.

Claims

1. A method of fabricating a semiconductor device, comprising the steps of:

forming a drain layer of a first conduction type on a surface of a semiconductor substrate of the first conduction type;

introducing an impurity of a second conduction type opposite to the first conduction type into an entire surface of said drain layer, thereby forming a channel layer;

forming a trench so as to penetrate said channel layer and reach said drain layer using a first mask;

forming a first insulating film on an inner wall of said trench and a surface of said channel layer;

forming a conductive layer on said first insulating film;

forming a second insulating film on said conductive layer;

patterning said second insulating film, said conductive layer, and said first insulating film with using a same second mask, to form a gate insulating film of said first insulating film, and a gate electrode of said conductive layer;

implanting an impurity of the first conduction type into a surface of said channel layer with using said gate electrode as a mask, thereby forming a impurity region of the first conduction type;

forming a third insulating film on an entire surface;

etching back said third insulating film to form a side wall insulator which covers side walls of said gate insulating film, said gate electrode, and said first insulating film;

forming a third mask having an opening located in a center of the impurity region and cover an entire surface except for the opening, before etching the impurity region;

etching the impurity region by using the third mask to form a recess to penetrate the impurity region and reach to the channel region, thereby forming a source region of the impurity region; and

implanting an impurity of the second conduction type into a bottom of said recess, with remaining said third mask, thereby forming a body contact region; and

removing said third mask; and

forming a second conductive layer which covers said source region, said body contact region, said side wall insulator, and said second insulating film, and patterning said second conductive layer by using a fourth mask, thereby forming a wiring layer.

2. The method of fabricating a semiconductor device according to claim 1, wherein said step of forming a source region is formed before the step of forming a trench.

3. The method of fabricating a semiconductor device according to claim 1, wherein the gate electrode is formed on the first insulating film to fill the trench and to cover the periphery of the trench formed on the channel region.

4. The method of fabricating a semiconductor device according to claim 1, wherein the opening of the third mask is formed smaller than a region of the impurity region between the adjacent sidewall insulators.

5. The method of fabricating a semiconductor device according to claim 1, wherein the source is separated from the trench.

6. The method of fabricating a semiconductor device according to claim 1, wherein an upper surface and a side surface of the source region are directly contacted with the wiring layer.