Semiconductor device with flowable insulation layer formed on capacitor and method for fabricating the same

• US 20050266650A1
• Filed: 12/10/2004
• Published: 12/01/2005
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Shin, Jong-Han, Ahn, Sang-Tae, Sheen, Dong-Sun, Song, Seok-Pyo
• Granted Patent: US 7,538,007 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/02137 the material comprising alkyl silsesquioxane, e.g. MSQ
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/3124 layers comprising hydrogen silsesquioxane
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor device includes: a capacitor formed on a predetermined portion of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and a metal interconnection line formed on the insulation layer. The method includes the steps of: forming a capacitor on a predetermined portion of a substrate; forming an insulation layer by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and forming a metal interconnection line on the insulation layer.

Claims

1. A semiconductor device, comprising:

a capacitor formed on a predetermined portion of a substrate;

an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and

a metal interconnection line formed on the insulation layer.

2. The semiconductor device of claim 1, wherein the flowable insulation layer is formed on the resulting structure and the undoped silicate glass layer is formed on the flowable insulation layer.

3. The semiconductor device of claim 1, wherein the undoped silicate glass layer is formed on the resulting structure including the capacitor and the flowable insulation layer is formed on the undoped silicate glass layer.

4. The semiconductor device of claim 2, wherein the flowable insulation layer is obtained by employing a spin on dielectric method by which a liquid source material is coated on the rotating substrate which is subsequently subjected to a thermal process.

5. The semiconductor device of claim 3, wherein the flowable insulation layer is obtained by employing a spin on dielectric method by which a liquid source material is coated on the rotating substrate which is subsequently subjected to a thermal process.

6. The semiconductor device of claim 2, wherein the flowable insulation layer is obtained by a low pressure chemical vapor deposition method using reaction sources such of silicon tetrahydride (SiH₄) and hydrogen peroxide (H₂O₂).

7. The semiconductor device of claim 3, wherein the flowable insulation layer is obtained by a low pressure chemical vapor deposition method using reaction sources such of silicon tetrahydride (SiH₄) and hydrogen peroxide (H₂O₂).

8. The semiconductor device of claim 4, wherein the liquid source material is one of hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ).

9. The semiconductor device of claim 5, wherein the liquid source material is one of HSQ and MSQ.

10. A method for fabricating a semiconductor device, comprising the steps of:

forming a capacitor on a predetermined portion of a substrate;

forming an insulation layer by stacking a flowable insulation layer and an undoped silicate glass layer on a resulting substrate structure including the substrate and the capacitor; and

forming a metal interconnection line on the insulation layer.

11. The method of claim 10, wherein the step of forming the insulation layer includes the steps of:

forming the flowable insulation layer on the resulting substrate structure with a thickness less than a height of the capacitor;

forming the undoped silicate glass layer on the flowable insulation layer by performing a plasma enhanced chemical vapor deposition method; and

planarizing the undoped silicate glass layer and the flowable insulation layer.

12. The method of claim 10, wherein the step of forming the insulation layer includes the steps of:

forming the undoped silicate glass layer on the resulting substrate structure with a thickness less than a height of the capacitor by performing a plasma enhanced vapor chemical deposition method;

forming the flowable insulation layer on the undoped silicate glass layer; and

planarizing the undoped silicate glass layer and the flowable insulation layer.

13. The method of claim 10, wherein the step of forming the insulation layer includes the steps of:

forming the undoped silicate glass layer on the resulting substrate structure with a thickness thicker than a height of the capacitor by performing a plasma enhanced chemical vapor deposition method;

planarizing the undoped silicate glass layer; and

forming the flowable insulation layer on the planarized undoped silicate glass layer.

14. The method of claim 10, wherein the step of forming the flowable insulation layer includes the steps of:

coating the substrate with a liquid source material selected from hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ) in the form of a thin layer by rotating the substrate; and

performing a thermal process to the coated thin layer.

15. The method of claim 10, wherein the step of forming the flowable insulation layer includes the steps of:

depositing a thin layer with use of a low pressure chemical vapor deposition method by using reaction sources of silicon tetrahydride (SiH₄) and hydrogen peroxide (H₂O₂); and

performing a thermal process to the thin layer.

16. The method of claim 10, wherein the thermal process proceeds in an atmosphere selected from a group consisting of oxygen (O₂), ozone (O₃), nitrogen (N₂), nitrogen oxide (N₂O) and a mixed gas of hydrogen (H₂) and oxygen (O₂) by employing one of a furnace thermal process and a rapid thermal process.

17. The method of claim 10, wherein the planarization process is performed by one of an etching process and a polishing process.