Interrupt generation circuit

• US 20050267668A1
• Filed: 05/25/2005
• Published: 12/01/2005
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Otsuji, Takashi
• Granted Patent: US 7,802,030 B2
• Time in Patent Office: Days
• US Class Current: 701/101
• CPC Class Codes: F02D 41/009 using means for generating position or synchronisation signals
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor

Abstract

The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt. If the count value of the main timer 104 is smaller than the value stored in the compare register 105 when the effective edge is detected, the interrupt determination circuit 106 immediately generates an interrupt.

Claims

1. An interrupt generation circuit comprising:

an edge detection unit that receives a periodic external signal from a monitored object and, upon detecting an effective edge of the external signal, generates an edge detection signal;

a main timer that counts a pulse signal and, when the edge detection signal is generated, clears a count value; and

an interrupt determination circuit that compares the count value of said main timer with a value stored in a compare register, in which a desired value is stored, for determining whether an interrupt is to be generated based on the comparison result,

wherein, when the edge detection signal is generated, said interrupt determination circuit generates an interrupt at a timing when the edge detection signal is generated if the count value of said main timer is smaller than the value stored in said compare register.

2. The interrupt generation circuit as defined by claim 1 wherein said interrupt determination circuit generates an interrupt when the count value of said main timer becomes equal to or larger than the value stored in said compare register if a compare enable signal is active, said compare enable signal being activated when the count value of said main timer is smaller than the value stored in said compare register, said compare enable signal being deactivated when the count value of said main timer is equal to or larger than the value stored in said compare register.

3. The interrupt generation circuit as defined by claim 1, further comprising:

a sub-timer that measures a time interval between a time when the edge detection signal is generated and a time when the next edge detection signal is generated; and

a count signal generation circuit that generates the pulse signal and, when the edge detection signal is generated, sets a period of the pulse signal based on the time interval between the effective edges measured by said sub-timer and on a division ratio 1/N where N representing an integer equal to or larger than 2.

4. The interrupt generation circuit as defined by claim 3 wherein the division ratio 1/N is set according to the time interval between the effective edges measured by said sub-timer.

5. The interrupt generation circuit as defined by claim 2, further comprising:

a sub-timer that measures a time interval between a time when the edge detection signal is generated and a time when the next edge detection signal is generated; and

a count signal generation circuit that generates the pulse signal and, when the edge detection signal is generated, sets a period of the pulse signal based on the time interval between the effective edges measured by said sub-timer and on a division ratio 1/N where N representing an integer equal to or larger than 2.

6. The interrupt generation circuit as defined by claim 5 wherein the division ratio 1/N is set according to the time interval between the effective edges measured by said sub-timer.