Configurable ready/busy control

• US 20050268025A1
• Filed: 05/27/2004
• Published: 12/01/2005
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Smith, Peter, Gorobets, Sergey
• Granted Patent: US 8,429,313 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory unit has a busy control system that includes a busy control register that may be written by a controller. The contents of the busy control register determine whether a signal is sent from the memory unit to the controller and, if so, which of a plurality of signals is sent. A signal may automatically be sent from a selected memory unit and masked from an unselected unit.

Claims

1. A memory unit in communication with a memory controller over a signal line in a memory system, comprising:

a buffered array of non-volatile memory cells; and

a control circuit that selects an output signal from the memory unit from a plurality of signals according to data bits in a control register, the plurality of signals including a first signal indicating whether the buffered memory array is in a first condition or a second condition and a second signal indicating whether the buffered memory array is in a third condition or a fourth condition.

2. The memory unit of claim 1 wherein the buffered array of non-volatile memory cells is on a first semiconductor die and the controller is on a second semiconductor die.

3. The memory unit of claim 1 wherein the buffered array of non-volatile memory cells comprises a cache connected to an array of non-volatile memory cells, wherein the first condition is a cache ready condition, the second condition is a cache busy condition, the third condition is an array ready condition and the fourth condition is an array busy condition.

4. The memory unit of claim 1 wherein the plurality of signals further includes a third signal that indicates that the memory unit is not busy, the third signal being selected by the control circuit in response to a data bit or bits in the control register when the memory unit is not selected by the controller.

5. A memory system having a buffered non-volatile memory array in communication with a controller, comprising:

a controller;

an array of non-volatile memory cells;

a cache connected to the array of non-volatile memory cells to hold data to be programmed to the array of non-volatile memory cells; and

a control register that selects an output signal to the controller from a plurality of signals including a first signal that indicates a ready/busy status of the array of non-volatile memory cells and a second signal that indicates a ready/busy status of the cache.

6. The memory system of claim 5 further comprising one or more additional buffered non-volatile memory arrays in communication with the controller via the signal line, an additional buffered non-volatile memory array having an additional control register that selects an additional signal.

7. A method of configuring a ready/busy signal from a plurality of integrated circuits to a controller based on selection of an integrated circuit by the controller, comprising:

when an autoselect mode is enabled for the plurality of integrated circuits, sending the ready/busy signal from the integrated circuit to the controller in response to selection of the integrated circuit by the controller; and

when the autoselect mode is enabled for the plurality of integrated circuits, masking the ready/busy signal from other ones of the plurality of integrated circuits when the integrated circuit is selected by the controller such that ready/busy signals from other ones of the plurality of integrated circuits are not sent to the controller.

8. The method of claim 7 wherein autoselect mode is permanently enabled for the plurality of integrated circuits.

9. The method of claim 7 wherein the autoselect mode may be disabled and, when the autoselect mode is disabled for the plurality of integrated circuits, a ready/busy signal is sent from the integrated circuit to the controller independently of whether the chip is selected.

10. A method of configuring a ready/busy signal from an integrated circuit to a controller, based on an autoselect feature and selection of the integrated circuit by the controller, comprising:

sending the ready/busy signal when the autoselect feature is not enabled and the integrated circuit is selected;

sending the ready/busy signal when the autoselect feature is not enabled and the integrated circuit is not selected;

sending the ready/busy signal when the autoselect feature is enabled and the integrated circuit is selected; and

masking the ready/busy signal when the autoselect feature is enabled and the integrated circuit is not selected.

11. The method of claim 10 wherein the autoselect feature is enabled when the contents of a control register indicate that the autoselect feature is enabled, the contents of the control register being written by the controller.

12. The method of claim 10 wherein the integrated circuit is selected when the most recently received command from the controller identifies the integrated circuit.

13. The method of claim 10 wherein the integrated circuit is selected when an external enabling signal is applied by a controller to the integrated circuit.

14. The method of claim 10 wherein the integrated circuit is selected when the most recently received command from the controller identifies the integrated circuit and an external enabling signal is applied by a controller to the integrated circuit.

15. An integrated circuit formed on a semiconductor die, the integrated circuit in communication with a controller that is not on the semiconductor die, comprising:

a first integrated circuit portion;

a control register having contents that are written by the controller; and

a second integrated circuit portion that receives a first input and a second input from the first integrated circuit portion and sends an output to a pin, the output selected from the first input and the second input according to the contents of the control register.

16. The integrated circuit of claim 15 wherein the first integrated circuit portion includes a memory array and a cache, the first input indicates a condition of the memory array and the second input indicates a condition of the cache.

17. The integrated circuit of claim 15 wherein the output is masked in response to the contents of the control register.

18. The integrated circuit of claim 17 wherein the output is masked when the integrated circuit is not selected by the controller