Method and system for terminating write commands in a hub-based memory system
First Claim
1. A method of processing write commands in a memory system having a memory hub architecture including a plurality of memory hubs coupled in a point-to-point architecture, the method comprising:
- applying a write command to a first hub in the system;
determining in the first hub whether the write command is directed to that hub;
when the determination indicates the write command is directed to the first hub, terminating downstream forwarding of the write data;
when the determination indicates the write command is not directed to the first hub, forwarding the write data downstream to a second hub; and
repeating the operations of determining through when the determination indicates the write command is not directed for all required memory hubs.
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Accused Products
Abstract
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command'"'"'s write data on a downstream output port adapted to be coupled to a downstream memory hub.
136 Citations
45 Claims
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1. A method of processing write commands in a memory system having a memory hub architecture including a plurality of memory hubs coupled in a point-to-point architecture, the method comprising:
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applying a write command to a first hub in the system;
determining in the first hub whether the write command is directed to that hub;
when the determination indicates the write command is directed to the first hub, terminating downstream forwarding of the write data;
when the determination indicates the write command is not directed to the first hub, forwarding the write data downstream to a second hub; and
repeating the operations of determining through when the determination indicates the write command is not directed for all required memory hubs. - View Dependent Claims (2, 3, 4, 5, 6, 12, 13)
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7. A method of operating a system memory having a memory hub architecture, the system memory including a plurality of memory modules coupled in series, each memory module including a memory hub, and the method comprising:
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detecting in each memory hub whether a write command is directed to the corresponding memory module;
when the operation of detecting indicates the write command is directed to the corresponding module, terminating the forwarding of the write data to downstream memory modules. - View Dependent Claims (8, 9, 10, 11)
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- 14. A memory hub adapted to receive downstream memory requests and operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory hub, and the memory hub operable in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices, and the hub operable in a second mode when the write command is not directed to the hub to provide the command on a downstream output port adapted to be coupled to a downstream memory hub.
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20. A memory module, comprising:
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a plurality of memory devices; and
a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A memory system, comprising:
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a system controller; and
a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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37. A computer system, comprising:
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a processor;
a system controller coupled to the processor;
an input device coupled to the processor through the system controller;
an output device coupled to the processor through the system controller;
a storage device coupled to the processor through the system controller; and
a plurality of memory modules coupled to the system controller, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45)
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Specification