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Erasure pointer error correction

  • US 20050268203A1
  • Filed: 05/26/2004
  • Published: 12/01/2005
  • Est. Priority Date: 05/26/2004
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments, where each data segment contains an ECC code; and

    a memory control circuit coupled to the at least one memory device, wherein the memory control circuit comprises, a data buffer, a host transfer circuit coupled to the data buffer, and two or more ECC generator/checkers circuits, where the data buffer and the two or more ECC generator/checker circuits are coupled to receive a selected read data segment.

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