Loop manipulation in a behavioral synthesis tool

• US 20050268271A1
• Filed: 11/10/2004
• Published: 12/01/2005
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Bowyer, Bryan Darrell, Takach, Andres R., Gutberlet, Peter Pius
• Granted Patent: US 7,412,684 B2
• Time in Patent Office: Days
• US Class Current: 716/102
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.

Claims

1. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:

detecting a first loop, wherein the first loop comprises a first item;

detecting a second loop, wherein the second loop comprises a second item that is dependent upon the first item; and

at least partially merging the first loop with the second loop.

2. The method of claim 1, wherein the first loop comprises a first subloop within a first parent loop.

3. The method of claim 2, wherein the second loop comprises a second subloop within a second parent loop.

4. The method of claim 2, wherein the second loop comprises a second subloop within the first parent loop.

5. The method of claim 1, wherein detecting the second loop comprises performing a dependency analysis on the second loop.

6. The method of claim 5, wherein performing the dependency analysis on the second loop comprises addressing at least one individual bit in an array accessed within the second loop.

7. A computer-readable medium having stored thereon computer-executable instructions for performing the method of claim 1.

8. A hardware circuit design containing a plurality of at least partially merged loops using the method of claim 1.

9. A networked computer method comprising:

receiving a plurality of dependent loops;

analyzing the plurality of dependent loops; and

merging the plurality of dependent loops.

10. A method comprising:

identifying loops within a source code representation of a hardware circuit, wherein a first loop is dependent upon a second loop; and

merging at least the first loop and second loop.

11. A system for designing integrated circuits, comprising:

an input device for receiving a source code description of an integrated circuit;

a processor for executing software;

software that identifies loops within the source code;

software that merges at least two loops together, wherein at least one of the loops comprises a dependent loop; and

an output device.

12. A method comprising:

receiving input code, wherein the input code comprises code relating to a plurality of loops, wherein at least one of the plurality of loops comprises a dependent loop;

processing the input code, wherein the processing comprises merging at least two of the plurality of loops; and

providing output code, wherein the output code comprises the at least two merged loops.

13. The method of claim 12, wherein the input code comprises C++ code.

14. The method of claim 12, wherein the output code comprises register transfer level (RTL) code.

15. In a user interface for a behavioral synthesis tool, a method comprising:

receiving a plurality of choices for setting a mergeable directive corresponding to a plurality of loops, wherein at least one of the plurality of loops comprises a dependent loop; and

selecting one of the plurality of choices.

16. The method of claim 15, wherein the plurality of choices comprises TRUE and FALSE.

17. The method of claim 15, further comprising receiving a default choice, wherein the default choice is based on a heuristic method.

18. In designing a hardware circuit, a method comprising:

identifying loops within a source code representation of a hardware design;

receiving via a graphical user interface (GUI) an indication to merge a plurality of the loops, wherein at least one of the plurality of loops comprises a dependent loop; and

merging the plurality of loops.

19. The method of claim 18, further comprising later receiving an indication to not merge the identified loops.

20. A method of creating a hardware circuit design, comprising:

selecting an option relating to a possible merging of a plurality of loops, wherein the plurality of loops comprises at least one dependent loop; and

receiving information regarding at least one impact the selected option might have on the hardware circuit design.

21. The method of claim 20, wherein one of the plurality of loops has already been merged with another of the plurality of loops.

22. A method of designing an integrated circuit, comprising:

identifying loops within a source code representation of a hardware design;

receiving via a graphical user interface (GUI) a request to analyze a potential merging of a plurality of the loops, wherein the plurality of loops comprises a first loop that is dependent upon at least a second loop; and

providing an analysis of the potential merging of the plurality of loops.

23. A method of designing an integrated circuit, comprising:

at least partially unrolling a first loop, wherein the first loop comprises a dependent loop; and

merging the first loop with a second loop.

24. A method of designing an integrated circuit, comprising:

merging a first loop with a second loop, wherein the second loop comprises a dependent loop; and

pipelining the first loop and the second loop.

25. A method, comprising:

identifying a first loop;

identifying a second loop, wherein the first loop is dependent on the second loop, and wherein the second loop is mergeable with the first loop; and

merging the first loop and the second loop together into a first merged loop.

26. The method of claim 25, further comprising:

identifying a third loop, wherein the third loop is mergeable with the first loop and the second loop; and

merging the first merged loop and the third loop together.

27. The method of claim 25, further comprising:

establishing a loop merging order; and

merging the first loop, second loop, and third loop in accordance with the loop merging order.