Trench type semiconductor device with reduced Qgd
First Claim
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1. A power semiconductor device comprising:
- a substrate having a first major surface and an opposing second major surface;
a drift region of one conductivity formed on said first major surface of said substrate;
a base region of another conductivity adjacent said drift region;
at least one trench extending through said base region and terminating at a depth below said base region;
a buried electrode disposed within said trench below said base region;
an insulation body interposed between said buried electrode and said trench walls;
an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;
at least one conductive region of said one conductivity formed in said body region;
a first power electrode electrically connected to said at least one conductive region;
a second power electrode electrically connected to said second major surface of said substrate;
a control electrode electrically connected to said gate electrode; and
a buried contact electrically connected to said buried electrode.
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Abstract
A trench type power semiconductor device which includes a buried electrode that is electrically connected to an electrode that can be biased to reach a voltage other than any of the other power electrodes.
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Citations
13 Claims
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1. A power semiconductor device comprising:
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a substrate having a first major surface and an opposing second major surface;
a drift region of one conductivity formed on said first major surface of said substrate;
a base region of another conductivity adjacent said drift region;
at least one trench extending through said base region and terminating at a depth below said base region;
a buried electrode disposed within said trench below said base region;
an insulation body interposed between said buried electrode and said trench walls;
an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;
at least one conductive region of said one conductivity formed in said body region;
a first power electrode electrically connected to said at least one conductive region;
a second power electrode electrically connected to said second major surface of said substrate;
a control electrode electrically connected to said gate electrode; and
a buried contact electrically connected to said buried electrode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of operating a power semiconductor device that includes:
- a substrate having a first major surface and an opposing second major surface;
a drift region of one conductivity formed on said first major surface of said substrate;
a base region of another conductivity adjacent said drift region;
at least one trench extending through said base region and terminating at a depth below said base region;
a buried electrode disposed within said trench below said base region;
an insulation body interposed between said buried electrode and said trench walls;
an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;
at least one conductive region of said one conductivity formed in said body region;
a first power electrode electrically connected to said at least one conductive region;
a second power electrode electrically connected to said second major surface of said substrate;
a control electrode electrically connected to said gate electrode; and
a buried electrode contact electrically connected to said buried electrode, comprising;
applying a first voltage to said first power electrode; and
applying a second voltage to said buried electrode, whereby said buried electrode is operated at a voltage different from said first voltage. - View Dependent Claims (8)
- a substrate having a first major surface and an opposing second major surface;
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9. A power semiconductor device comprising:
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a silicon substrate of one conductivity having a first major surface and an opposing second major surface;
a drift region of said one conductivity formed on said first major surface of said substrate;
a base region of another conductivity adjacent said drift region;
at least one trench extending through said base region and terminating at a depth below said base region;
a buried electrode disposed within said trench below said base region;
an insulation body interposed between said buried electrode and said trench walls;
an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;
at least one source region of said one conductivity formed in said body region;
a source electrode electrically connected to said at least one source region;
a drain electrode electrically connected to said second major surface of said substrate;
a gate contact electrically connected to said gate electrode; and
a buried electrode contact electrically connected to said buried electrode. - View Dependent Claims (10, 11, 12, 13)
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Specification