Trench type semiconductor device with reduced Qgd

• US 20050269630A1
• Filed: 06/01/2005
• Published: 12/08/2005
• Est. Priority Date: 06/04/2004
• Status: Abandoned Application

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG), US Wind Farming, Inc.
• Original Assignee: US Wind Farming, Inc.
• Inventors: Cao, Jianjun
• Application Number:
  US11/142,034
• Publication Number:
  US 20050269630A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power semiconductor device which includes a buried electrode that is electrically connected to an electrode that can be biased to reach a voltage other than any of the other power electrodes.

Claims

1. A power semiconductor device comprising:

a substrate having a first major surface and an opposing second major surface;

a drift region of one conductivity formed on said first major surface of said substrate;

a base region of another conductivity adjacent said drift region;

at least one trench extending through said base region and terminating at a depth below said base region;

a buried electrode disposed within said trench below said base region;

an insulation body interposed between said buried electrode and said trench walls;

an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;

at least one conductive region of said one conductivity formed in said body region;

a first power electrode electrically connected to said at least one conductive region;

a second power electrode electrically connected to said second major surface of said substrate;

a control electrode electrically connected to said gate electrode; and

a buried contact electrically connected to said buried electrode.

2. A device according to claim 1, wherein said first power electrode is a source electrode;

said second power electrode is a drain electrode, and said control electrode is a gate electrode.

3. A device according to claim 1, wherein said buried electrode is comprised of polysilicon.

4. A device according to claim 1, wherein said insulation body is comprised of an oxide.

5. A device according to claim 1, wherein said insulation body is comprised of silicon dioxide.

6. A device according to claim 1, wherein said insulated gate electrode includes gate insulation adjacent said base region and wherein said insulation body is thicker than said gate insulation.

7. A method of operating a power semiconductor device that includes:

a substrate having a first major surface and an opposing second major surface;

a drift region of one conductivity formed on said first major surface of said substrate;

a base region of another conductivity adjacent said drift region;

at least one trench extending through said base region and terminating at a depth below said base region;

a buried electrode disposed within said trench below said base region;

an insulation body interposed between said buried electrode and said trench walls;

an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;

at least one conductive region of said one conductivity formed in said body region;

a first power electrode electrically connected to said at least one conductive region;

a second power electrode electrically connected to said second major surface of said substrate;

a control electrode electrically connected to said gate electrode; and

a buried electrode contact electrically connected to said buried electrode, comprising;

applying a first voltage to said first power electrode; and

applying a second voltage to said buried electrode, whereby said buried electrode is operated at a voltage different from said first voltage.

8. A device according to claim 7, wherein said second voltage is positive with respect to said first voltage.

9. A power semiconductor device comprising:

a silicon substrate of one conductivity having a first major surface and an opposing second major surface;

a drift region of said one conductivity formed on said first major surface of said substrate;

a base region of another conductivity adjacent said drift region;

at least one trench extending through said base region and terminating at a depth below said base region;

a buried electrode disposed within said trench below said base region;

an insulation body interposed between said buried electrode and said trench walls;

an insulated gate electrode disposed in said trench and over said buried electrode in said trench and spanning the entire thickness of said base region;

at least one source region of said one conductivity formed in said body region;

a source electrode electrically connected to said at least one source region;

a drain electrode electrically connected to said second major surface of said substrate;

a gate contact electrically connected to said gate electrode; and

a buried electrode contact electrically connected to said buried electrode.

10. A device according to claim 9, wherein said buried electrode is comprised of polysilicon.

11. A device according to claim 9, wherein said insulation body is comprised of an oxide.

12. A device according to claim 9, wherein said insulation body is comprised of silicon dioxide.

13. A device according to claim 9, wherein said insulated gate electrode includes gate insulation adjacent said base region and wherein said insulation body is thicker than said gate insulation.