Liquid crystal display device and fabricating method thereof

• US 20050269638A1
• Filed: 06/03/2005
• Published: 12/08/2005
• Est. Priority Date: 06/05/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Ji No, Kwack, Hee Young, Jung, Tae Yong
• Granted Patent: US 7,439,586 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the substrate; at least one aperture through the insulating film and arranged within the at least one dummy area; and at least one post arranged within the at least one aperture.

Claims

1. A base thin film transistor (TFT) array substrate, comprising:

a substrate;

a plurality of array areas on the substrate;

at least one dummy area on the substrate and between the plurality of array areas;

an insulating film on the substrate;

at least one aperture through the insulating film and arranged within the at least one dummy area; and

at least one post arranged within the at least one aperture.

2. The base TFT array substrate of claim 1, further comprising a transparent conductive material within the aperture.

3. The base TFT array substrate of claim 1, wherein the insulating film includes:

a gate insulating film; and

a passivation film.

4. The base TFT array substrate of claim 1, wherein the at least one post comprises insulating material.

5. The base TFT array substrate of claim 4, wherein the at least one post includes:

a gate insulating film; and

a passivation film.

6. The base TFT array substrate of claim 1, further comprising a dummy sealant pattern on the at least one post.

7. The base TFT array substrate of claim 6, wherein the at least one post includes a plurality of holes.

8. The base TFT array substrate of claim 7, further comprising a transparent conductive material formed within the plurality of holes and the aperture.

9. The base TFT array substrate of claim 7, wherein a width of each hole is less than a width of the dummy sealant pattern formable over the at least one aperture.

10. The base TFT array substrate of claim 1, further comprising a plurality of TFTs within each array area.

11. A method of fabricating a display device, comprising:

forming a plurality of array areas on a first substrate, wherein the plurality of array areas are separated by at least one dummy area;

forming an insulating film on the first substrate;

forming at least one aperture through a portion of the insulating film arranged within the at least one dummy area; and

forming at least one post arranged within the at least one aperture.

12. The method of claim 11, further comprising forming the at least one aperture and the at least one post simultaneously.

13. The method of claim 12, wherein forming the hole and the opening portion includes:

forming a photo-resist pattern on the insulating film;

etching the insulating film using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern; and

removing the photo-resist pattern and portions of the transparent conductive film formed thereon.

14. The method of claim 11, wherein forming the insulating film includes:

forming a gate insulating film; and

a passivation film.

15. The method of claim 11, wherein the at least one post comprises insulating material.

16. The method of claim 15, wherein the at least one post includes:

a gate insulating film; and

a passivation film.

17. The method of claim 11, further comprising bonding a second substrate to the first substrate.

18. The method of claim 17, wherein the bonding includes providing at least one dummy sealant pattern between the first and second substrates, wherein the at least one dummy sealant pattern contacts the at least one post.

19. The method of claim 18, further comprising forming a plurality of holes within the at least one post.

20. The method of claim 19, wherein a width of each hole is less than a width of the dummy sealant pattern formable over the at least one aperture.

21. The method of claim 11, further comprising forming a plurality of thin film transistors (TFTs) within each array area.

22. The method of claim 19, wherein a transparent conductive material is formed within the plurality of holes and the aperture.