Semiconductor device having stress and its manufacture method

• US 20050269650A1
• Filed: 10/22/2004
• Published: 12/08/2005
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Pidin, Sergey
• Granted Patent: US 7,262,472 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device has: active regions including a p-type active region; an insulated gate electrode structure formed on each of the active regions, and having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of the insulated gate electrode structures; source/drain regions having extension regions having the opposite conductivity type to that of the active region and formed on both sides of the insulated gate electrode structures and source/drain diffusion layers having the opposite conductivity type and formed in the active regions outside of the side wall spacers; first recess regions formed by digging down the n-type source/drain regions in the p-type active region from surfaces of the n-type source/drain regions; and a first nitride film having tensile stress formed covering the p-type active region and burying the first recess regions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a plurality of active regions including a p-type active region;

an insulated gate electrode structure formed on each of said active regions, said insulated gate electrode structure having a gate insulating film and a gate electrode formed thereon;

side wall spacers formed on side walls of each of said insulated gate electrode structures;

source/drain regions having extension regions having a conductivity type opposite to a conductivity type of each of said active regions and formed in said active regions on both sides of each of said insulated gate electrode structures and source/drain diffusion layers having the conductivity type opposite to the conductivity type of each of said active regions and formed in said active regions outside of said side wall spacers;

first recess regions formed by digging down n-type source/drain regions in said p-type active region from surfaces of said n-type source/drain regions; and

a first nitride film having a tensile stress formed covering said p-type active region and burying said first recess regions.

2. A semiconductor device according to claim 1, wherein said first recess region has a region creeping under adjacent one of said side wall spacers.

3. A semiconductor device according to claim 2, wherein a length of the region of said first recess region creeping under said adjacent side wall spacer is 1 nm to 20 nm.

4. A semiconductor device according to claim 1, wherein said plurality of active regions include also an n-type active region, and the semiconductor device further comprises:

second recess regions formed by digging down said source/drain regions in said n-type active region from surfaces of said source/drain regions; and

a second nitride film having a compressive stress formed covering said n-type active region and burying said second recess regions.

5. A semiconductor device according to claim 4, wherein said first and second recesses have regions creeping under adjacent one of said side wall spacers.

6. A semiconductor device according to claim 5, wherein a length of said region creeping under said side wall spacer is 1 nm to 20 nm.

7. A semiconductor device according to claim 5, wherein lengths of said regions creeping under said side wall spacers are different.

8. A semiconductor device according to claim 4, wherein said first nitride film is a nitride film formed by thermal CVD and said second nitride film is a nitride film formed by plasma CVD.

9. A semiconductor device according to claim 1, wherein a depth of said first recess region is shallower than a depth of said extension region.

10. A semiconductor device according to claim 9, wherein the depth of said first recess region is in a range from 1 nm to 20 nm.

11. A semiconductor device according to claim 1, wherein said plurality of active regions include also an n-type active region, said n-type active region has no recess region, and said first nitride film covers also said n-type active region.

12. A semiconductor device according to claim 11, wherein said first recess region has a region creeping under adjacent one of said side wall spacers.

13. A semiconductor device according to claim 2, wherein a length of the region of said first recess region creeping under said adjacent side wall spacer is 1 nm to 20 nm.

14. A semiconductor device manufacture method, comprising the steps of:

(a) preparing a semiconductor substrate having a plurality of active regions including a p-type active region;

(b) forming an insulated gate electrode structure on each of said active regions, said insulated gate electrode structure having a gate insulating film and a gate electrode formed thereon;

(c) implanting impurities of a conductivity type opposite to a conductivity type of each of said active regions in said active regions on both sides of said insulated gate electrode structure to form extension regions;

(d) forming side wall spacers on side walls of each of said insulated gate electrode structures;

(e) digging said extension regions in said p-type active region from surfaces of said extension regions to form first recesses;

(f) implanting impurities of the conductivity type opposite to the conductivity type of said active region in said active regions outside of said insulated gate electrode structure and said side wall spacers to form source/drain diffusion layers; and

(g) forming a first nitride film having a tensile stress, said nitride film covering said p-type active region and burying said first recess regions.

15. A semiconductor device manufacture method according to claim 14, wherein said step (e) forms said first recess regions having regions creeping under said adjacent side wall spacers.

16. A semiconductor device manufacture method according to claim 15, wherein said step (e) includes anisotropic etching and isotropic etching.

17. A semiconductor device manufacture method according to claim 14, wherein said step (g) forms said first nitride film by thermal CVD.

18. A semiconductor device manufacture method according to claim 14, wherein said plurality of active regions include also an n-type active region, said step (e) forms at a same time second recess regions in said n-type active region, and said step (g) forms at a same time said first nitride film covering said n-type active region, wherein the semiconductor device manufacture method further comprises the steps of:

(h) removing said first nitride film on said n-type active region; and

(i) forming a second nitride film having a compressive stress and covering said n-type active region.

19. A semiconductor device manufacture method according to claim 18, wherein said step (i) forms said second nitride film by plasma CVD.

20. A semiconductor device manufacture method according to claim 14, wherein said plurality of active regions include also an n-type active region, said step (e) does not form any recess regions in said n-type active region, and said step (g) forms at a same time said first nitride film having tensile stress covering said n-type active region.