On chip transformer isolator

• US 20050269657A1
• Filed: 06/03/2004
• Published: 12/08/2005
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Dupuis, Timothy
• Granted Patent: US 7,447,492 B2
• Time in Patent Office: Days
• US Class Current: 257/446
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 19/08 Transformers having magnetic bias, e.g. for handling pulses
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An integrated circuit having voltage isolation capabilities includes a first area of the integrated circuit containing functional circuitry that is located in the substrate of the integrated circuit. A second area of the integrated circuit contains an integrated RF isolation circuitry for voltage isolating the functional circuitry. The RF isolation circuitry is located in the metal layers of the integrated circuit.

Claims

1. An integrated circuit having voltage isolation capabilities, comprising:

a first area of the integrated circuit containing functional circuitry, the functional circuitry located in a substrate of the integrated circuit; and

a second area of the integrated circuit containing integrated RF isolation circuitry for voltage isolating the functional circuitry, the RF isolation circuitry located in metal layers of the integrated circuit.

2. The integrated circuit of claim 1, wherein the RF isolation circuitry further comprises:

a first coil located on a first metal layer, the first coil connected to the functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil.

3. The integrated circuit of claim 2, wherein the RF isolation circuitry further comprises:

first and second terminals located on a third metal layer below the first metal layer for interconnecting the first coil with the functional circuitry.

4. The integrated circuit of claim 2, wherein runs of the first coil are diagonally offset from runs of the second coil.

5. The integrated circuit of claim 2, wherein the first metal layer and the second metal layer are separated by at least one dielectric layer.

6. The integrated circuit of claim 1, wherein the first metal layer is the metal one layer and the second metal layer comprises the metal five layer.

7. The integrated circuit of claim 2 further including:

a first pad connected to a first end of the second coil and located within the second coil; and

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil.

8. The integrated circuit of claim 1, wherein the RF isolation circuitry further comprises a plurality of transformers, each of the plurality of transformers comprising:

a first coil located on a first metal layer, the first coil connected to the functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil.

9. The integrated circuit of claim 8 wherein each transformer further includes:

a first pad connected to a first end of the second coil and located within the second coil;

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil; and

wherein at least two of the plurality of transformers share the second pad for the second coil.

14. The integrated circuit of claim 1, wherein the at least one RF isolation interface further comprises a plurality of RF isolation interfaces, each of the plurality of RF isolation interfaces comprising:

a first coil located on a first metal layer, the first coil connected to the functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil.

15. The integrated circuit of claim 8 wherein each of the plurality of RF isolation interfaces further includes:

a first pad connected to a first end of the second coil and located within the second coil;

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil; and

wherein at least two of the plurality of RF isolation interfaces share the second pad for the second coil.

10. An integrated circuit having voltage isolation capabilities, comprising:

a first area of the integrated circuit containing functional circuitry, the functional circuitry located in a substrate of the integrated circuit; and

a second area of the integrated circuit containing integrated at least one RF isolation interface for voltage isolating the functional circuitry, the at least one RF isolation interface located in metal layers of the integrated circuit above the substrate, the at least one RF isolation interface comprising;

a first coil located on a first metal layer, the first coil connected to the functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil;

first and second terminals located on a third metal layer below the first metal layer for interconnecting the first coil with the functional circuitry;

a first pad connected to a first end of the second coil and located within the second coil; and

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil.

11. The integrated circuit of claim 10, wherein runs of the first coil are diagonally offset from runs of the second coil.

12. The integrated circuit of claim 10, wherein the first metal layer and the second metal layer are separated by at least one dielectric layer.

13. The integrated circuit of claim 10, wherein the first metal layer is the metal one layer and the second metal layer comprises the metal five layer.

16. An integrated circuit having voltage isolation capabilities, comprising:

a first area of the integrated circuit containing a first group of functional circuitry, the first group of functional circuitry located in a substrate of the integrated circuit;

a second area of the integrated circuit containing a second group of functional circuitry, the second group of functional circuitry located in the substrate of the integrated circuit; and

a second area of the integrated circuit containing integrated RF isolation circuitry for voltage isolating the first group of functional circuitry from the second group of functional circuitry, the RF isolation circuitry located in metal layers of the integrated circuit.

17. The integrated circuit of claim 16, wherein the RF isolation circuitry further comprises:

a first coil located on a first metal layer, the first coil connected to the first group of functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil

a third coil located on the first metal layer, the third coil connected to the second group of functional circuitry; and

a fourth coil located on the second metal layer above the first metal layer and substantially non-overlapping the third coil, the fourth coil electromagnetically coupled to the third coil and connected to the second coil.

18. The integrated circuit of claim 17, wherein the RF isolation circuitry further comprises:

first and second terminals located on a third metal layer below the first metal layer for interconnecting the first coil with the functional circuitry; and

third and fourth terminals located on the third metal layer below the first metal layer for interconnecting the first coil with the second group of functional circuitry.

19. The integrated circuit of claim 17, wherein runs of the first coil are diagonally offset from runs of the second coil.

20. The integrated circuit of claim 17, wherein runs of the third coil are diagonally offset from runs of the fourth coil.

21. The integrated circuit of claim 17, wherein the first metal layer and the second metal layer are separated by at least one dielectric layer.

22. The integrated circuit of claim 16, wherein the first metal layer is the metal one layer and the second metal layer comprises the metal five layer.

23. The integrated circuit of claim 17 further including:

a first pad connected to a first end of the second coil and located within the second coil; and

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil;

a third pad connected to a first end of the fourth coil and located within the fourth coil; and

a fourth pad connected to a second end of the fourth coil and located substantially near an edge of the fourth coil.

24. The integrated circuit of claim 16, wherein the RF isolation circuitry further comprises a plurality of channels, each of the plurality of channels comprising:

a first coil located on a first metal layer, the first coil connected to the first group of functional circuitry;

a second coil located on a second metal layer above the first metal layer and substantially non-overlapping the first coil, the second coil electromagnetically coupled to the first coil

a third coil located on the first metal layer, the third coil connected to the second group of functional circuitry; and

a fourth coil located on the second metal layer above the first metal layer and substantially non-overlapping the third coil, the fourth coil electromagnetically coupled to the third coil and connected to the second coil.

25. The integrated circuit of claim 23 wherein each transformer further includes:

a first pad connected to a first end of the second coil and located within the second coil; and

a second pad connected to a second end of the second coil and located substantially near an edge of the second coil;

a third pad connected to a first end of the fourth coil and located within the fourth coil; and

a fourth pad connected to a second end of the fourth coil and located substantially near an edge of the fourth coil; and

wherein at least two of the plurality of transformers share the second pad for the second coil and share the fourth pad for the fourth coil.

26. An integrated circuit with high voltage isolation interface, comprising:

a semiconductor substrate;

a functional circuit integrally formed on said substrate for processing at least a single bit of digital data;

an isolator integrally formed on said substrate for interfacing with said functional circuit for allowing external data from a potentially high voltage circuit relative to said functional circuit to be input across said isolator to said functional circuit or for allowing data to be output from said functional circuit across said isolator to said potentially high voltage circuit.

27. The integrated circuit of claim 26, wherein said isolator comprises:

a first conductive element formed on said semiconductor substrate and conductively interfaced with said functional circuit;

a second conductive element formed on said semiconductor substrate and providing a conductive interface to the exterior of said semiconductor substrate; and

said first conductive element electrically isolated from said second conductive element to allow only electromagnetic coupling there between, such that a portion of the electromagnetic spectral energy can be coupled there across.

28. The integrated circuit of claim 27, wherein said first conductive element is electrically isolated from said second conductive element by a layer of insulating material.

29. The integrated circuit of claim 28, wherein said insulating material comprises silicon dioxide.

30. The integrated circuit of claim 29, wherein said first conductive element and said second conductive element are fabricated from metal layers utilized in the fabrication of said functional circuit.

31. The integrated circuit of claim 27 wherein said functional circuit is formed on said semiconductor substrate in an area separate from said isolator.

32. The integrated circuit of claim 27, wherein said functional circuit is operable to operate in either a data receive mode or a data transmission mode.

33. The integrated circuit of claim 32, wherein said functional circuit includes a driver for driving said first conductive element in the data transmission mode.

34. The integrated circuit of claim 33, wherein said isolator operates over a finite bandwidth and said driver is operable to drive said first conductive element such tat the spectral energy output thereby is concentrated substantially within said bandwidth.

35. The integrated circuit of claim 34, wherein said driver is operable to modulate the spectral energy output thereby with the data to be transmitted.

36. The integrated circuit of claim 35, wherein said modulation comprises providing an output for one data state and not providing an output for the other data state in a binary system.

37. The integrated circuit of claim 36, wherein said first conductive element has an impedance that has an inductive element associated therewith.

38. The integrated circuit of claim 37, wherein said first inductive element comprises a primary coil formed on one layer of said semiconductor substrate and said second inductive element comprises a secondary coil formed on a second layer of said semiconductor substrate and separated therefrom by a layer of dielectric.

39. The integrated circuit of claim 27, wherein said first inductive element comprises a primary coil formed on one layer of said semiconductor substrate and said second inductive element comprises a secondary coil formed on a second layer of said semiconductor substrate and separated therefrom by a layer of dielectric.

40. The integrated circuit of claim 39, wherein said isolator is disposed on a portion of said semiconductor substrate not overlying said functional circuit.