V.42bis standalone hardware accelerator and architecture of construction

• US 20050270188A1
• Filed: 08/17/2004
• Published: 12/08/2005
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chu, Hon Fai
• Granted Patent: US 7,079,054 B2
• Time in Patent Office: Days
• US Class Current: 341/50
• CPC Class Codes: H03M 7/3088 employing the use of a dictionary, e.g. LZ78
• CPC Class Codes: Y10S 707/99942 Manipulating data structure, e.g. compression, compaction, compilation

Abstract

Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.

Claims

1. A method for on-chip processing of data, the method comprising:

generating a plurality of data processing commands for data compression; and

encoding a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression.

2. The method according to claim 1, wherein said plurality of data processing commands comprise at least one of a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and a register compare command.

3. The method according to claim 1, further comprising storing said generated plurality of data processing commands.

4. The method according to claim 3, further comprising decoding at least a portion of said stored data processing commands.

5. The method according to claim 4, further comprising sequencing said decoded at least a portion of said stored data processing commands.

6. The method according to claim 1, further comprising acquiring said first string of characters from a character space.

7. The method according to claim 6, further comprising matching said acquired first string of characters with at least one existing codeword.

8. The method according to claim 7, further comprising storing said matched at least one existing codeword into a codeword space.

9. The method according to claim 7, further comprising generating a new codeword corresponding to said acquired first string of characters, if said acquired first string of characters does not match said at least one existing codeword.

10. The method according to claim 1, further comprising generating a plurality of data processing commands for data decompression.

11. The method according to claim 10, further comprising decoding at least one codeword in one operating cycle utilizing said generated plurality of data processing commands for data decompression.

12. The method according to claim 11, further comprising matching said at least one codeword with a second string of characters.

13. The method according to claim 11, further comprising storing said matched second string of characters into a character space.

14. A machine-readable storage having stored thereon, a computer program having at least one code section for on-chip processing of data, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

generating a plurality of data processing commands for data compression; and

encoding a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression.

15. The machine-readable storage according to claim 14, wherein said plurality of data processing commands comprise at least one of a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and a register compare command.

16. The machine-readable storage according to claim 14, further comprising code for storing said generated plurality of data processing commands.

17. The machine-readable storage according to claim 16, further comprising code for decoding at least a portion of said stored data processing commands.

18. The machine-readable storage according to claim 17, further comprising sequencing said decoded at least a portion of said stored data processing commands.

19. The machine-readable storage according to claim 14, further comprising code for acquiring said first string of characters from a character space.

23. The machine-readable storage according to claim 14, further comprising code for generating a plurality of data processing commands for data decompression.

24. The machine-readable storage according to claim 23, further comprising code for decoding at least one codeword in one operating cycle utilizing said generated plurality of data processing commands for data decompression.

25. The machine-readable storage according to claim 24, further comprising code for matching said at least one codeword with a second string of characters.

26. The machine-readable storage according to claim 25, further comprising code for storing said matched second string of characters into a character space.

27. A system for on-chip processing of data, the system comprising:

an accelerator that generates a plurality of data processing commands for data compression; and

said accelerator encodes a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression.

20. The machine-readable storage according to claim 29, further comprising code for matching said acquired first string of characters with at least one existing codeword.

21. The machine-readable storage according to claim 20, further comprising code for storing said matched at least one existing codeword into a codeword space.

22. The machine-readable storage according to claim 20, further comprising code for generating a new codeword corresponding to said acquired first string of characters, if said acquired first string of characters does not match said at least one existing codeword.

28. The system according to claim 27, wherein said plurality of data processing commands comprise at least one of a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and a register compare command.

29. The system according to claim 27, wherein said accelerator stores said generated plurality of data processing commands.

30. The system according to claim 29, wherein said accelerator decodes at least a portion of said stored data processing commands.

31. The system according to claim 30, wherein said accelerator sequences said decoded at least a portion of said stored data processing commands.

32. The system according to claim 27, wherein said accelerator acquires said first string of characters from a character space.

33. The system according to claim 32, wherein said accelerator matches said acquired first string of characters with at least one existing codeword.

34. The system according to claim 33, wherein said accelerator stores said matched at least one existing codeword into a codeword space.

35. The system according to claim 33, wherein said accelerator generates a new codeword corresponding to said acquired first string of characters, if said acquired first string of characters does not match said at least one existing codeword.

36. The system according to claim 27, wherein said accelerator generates a plurality of data processing commands for data decompression.

37. The system according to claim 36, wherein said accelerator decodes at least one codeword in one operating cycle utilizing said generated plurality of data processing commands for data decompression.

38. The system according to claim 37, wherein said accelerator matches said at least one codeword with a second string of characters.

39. The system according to claim 38, wherein said accelerator stores said matched second string of characters into a character space.