ELECTRONIC DEVICES WITH SMALL FUNCTIONAL ELEMENTS SUPPORTED ON A CARRIER

• US 20050270752A1
• Filed: 09/27/2004
• Published: 12/08/2005
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: Glenn Gengei, Rodger Green Stewart, Thomas Lloyd Credelle, William Hill Joseph
• Inventors: Gengei, Glenn, Credelle, Thomas Lloyd, Stewart, Roger Green, Joseph, William Hill
• Granted Patent: US 6,985,361 B2
• Time in Patent Office: Days
• US Class Current: 361/736
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: G06K 19/07752 using an interposer
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: G06K 19/07783 the coil being planar
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15155 : the shape of the recess being other than a cuboid
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01Q 1/2208 : associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems methods or arrangements for sensing record carriers, e.g. for reading patterns G06K7/00; record carrier for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H01Q 7/00 : Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 3/222 : Completing of printed circuits by adding non-printed jumper connections printed jumper connections H05K3/4685
• CPC Class Codes: H05K 3/321 : by conductive adhesives
• CPC Class Codes: Y10T 29/49002 : Electrical device making
• CPC Class Codes: Y10T 29/49016 : Antenna or wave energy "plumbing" making
• CPC Class Codes: Y10T 29/49018 : with other electrical component
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

Methods and apparatuses for an electronic assembly. The electronic assembly has a first object created and separated from a host substrate. The first object has a first electrical circuitry therein. A carrier substrate is coupled to the first object wherein the first object is being recessed below a surface of the carrier substrate. The carrier substrate further includes a first carrier connection pad and a second carrier connection pad that interconnect with the first object using metal connectors. A receiving substrate, which is substantially planar, including a second electrical circuitry, a first receiving connection pad, and a second receiving connection pad that interconnect with the second electrical circuitry using the metal connectors. The carrier substrate is coupled to the receiving substrate using the connection pads mentioned.

Claims

1. An electronic assembly comprising:

a first object created and separated from a host substrate, said first object having a first electrical circuitry therein;

a carrier substrate, said first object deposited in said carrier substrate, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that interconnect with said first object using metal connectors, said first object further being recessed below a surface of said carrier substrate, wherein said carrier substrate includes a recessed region complimentary to said first object for depositing said first object using a fluidic self assembly (FSA) process; and

a receiving substrate including a second electrical circuitry which is substantially planar, said receiving substrate further including a first receiving connection pad, and a second receiving connection pad that interconnect with said second electrical circuitry using said metal connectors, said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad providing an electrical connection between said first electrical circuitry and said second electrical circuitry.

2. An electronic assembly as in claim 1 further comprising an insulation layer, said insulation layer insulating said first electronic circuitry and said second electronic circuitry.

3. An electronic assembly as in claim 2 wherein said second electrical circuitry is an antenna.

4. An electronic assembly as in claim 3 wherein said carrier substrate is a flexible strap and wherein said first object comprises a radio frequency circuitry for use in a radio frequency identification tag.

5. An electronic assembly as in claim 1 wherein said carrier substrate is flexible.

6. An electronic assembly as in claim 1 wherein said first object is an integrated circuitry.

7. An electronic assembly as in claim 1 further comprising at least one second object, said second object being recessed within said carrier substrate and being interconnected to said first to said first object using said metal connectors.

8. An electronic assembly as in claim 7 further comprising at least one third object, said third object being coupled to said receiving substrate and being interconnected to said second electrical circuitry using said metal connectors.

9. An electronic assembly as in claim 1 wherein said second electrical circuitry is a printed circuit board.

10. An electronic assembly as in claim 1 wherein said electronic assembly is a multi-feature-size structure in which said carrier substrate is at least five times larger in feature size than said first object and wherein said carrier substrate is at least five times smaller in feature size than said receiving substrate.

11. An electronic assembly as in claim 5 wherein said electronic assembly is a multi-feature-size structure in which said carrier substrate is at least five times larger in feature size than said first object and wherein said carrier substrate is at least five times smaller in feature size than said receiving substrate.

12. An electronic assembly as in claim 11 wherein said carrier substrate couples to said first object through a fluidic self-assembly process.

13. An electronic assembly as in claim 1 wherein said carrier substrate couples to said first object through a fluidic self-assembly process.

14. An electronic assembly as in claim 1 wherein said first carrier connection pad and said second carrier connection pad are the only carrier connection pads on said carrier substrate.

15. An electronic assembly as in claim 12 wherein a conductive adhesive material is used to couple said first carrier connection pad to said first receiving connection pad and said second carrier connection pad to said second receiving connection pad.

16. (canceled)

17. (canceled)

18. (canceled)

19. (canceled)

20. An electronic assembly comprising:

a first object created and separated from a host substrate, said first object having a first electrical circuitry therein;

a carrier substrate, said first object deposited in said carrier substrate, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that forms a first interconnection with said first object using metal conductors, wherein said carrier substrate includes a recessed region complimentary to said first object for depositing said first object using a fluidic self assembly (FSA) process and wherein said first object is deposited below a surface of said carrier substrate;

a receiving substrate including a second electrical circuitry which is substantially planar, said receiving substrate further including a first receiving connection pad, and a second receiving connection pad that forms a second interconnection with said second electrical circuitry using said metal conductors, said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad providing an electrical connection between said first electrical circuitry and said second electrical circuitry; and

said first electrical circuitry, said first interconnection, and said second interconnection are essentially coplanar.

21. An electronic assembly as in claim 20 wherein each of said first electrical circuitry, said first interconnection, and said second interconnection forms a plane and each of said plane is separated from one another by less than ten micrometers.

22. An electronic assembly as in claim 21 wherein said carrier substrate is flexible.

23. A method of making an electronic assembly comprising:

creating and separating a first object from a host substrate, said first object having a first electrical circuitry therein;

depositing said first object in a carrier substrate, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that interconnect with said first object using metal conductors, said first object further being recessed below a surface of said carrier substrate, wherein said carrier substrate includes a recessed region complimentary to said first object; and

integrating said carrier substrate to a receiving substrate including a second electrical circuitry which is substantially planar and including a first receiving connection pad, and a second receiving connection pad that interconnect with said second electrical circuitry using said metal conductors, said integrating providing an electrical connection between said first electrical circuitry and said second electrical circuitry wherein said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad.

24. A method of making an electronic assembly as in claim 23 further comprising coating an insulation layer over said metal conductors, said insulation layer to insulate said first electronic circuitry and said second electronic circuitry.

25. A method of making an electronic assembly as in claim 24 further comprising configuring said second electrical circuitry to be an antenna.

26. A method of making an electronic assembly as in claim 25 further comprising configuring said carrier substrate to be a flexible strap wherein said first object comprises a radio frequency circuitry for use in a radio frequency identification tag.

27. A method of making an electronic assembly as in claim 23 further comprising configuring said first object to be an integrated circuitry.

28. A method of making an electronic assembly as in claim 23 further comprising configuring said second electrical circuitry to be a printed circuit board.

29. A method of making an electronic assembly as in claim 23 further comprising making said electronic assembly a multi-feature-size structure wherein said carrier substrate is at least five times larger in feature size than said first object and said carrier substrate is at least five times smaller in feature size than said receiving substrate.

30. A method of making an electronic assembly as in claim 23 wherein said coupling of said carrier substrate to said first functional object is accomplished through a fluidic self-assembly process.

31. A method of making an electronic assembly comprising:

creating and separating a first object from a host substrate, said first object having a first electrical circuitry therein;

depositing said first object into a recessed region in a carrier substrate, said first object being recessed below a surface of said carrier substrate, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that interconnect with said first object using metal conductors;

integrating said carrier substrate to a receiving substrate including a second electrical circuitry which is substantially planar and including a first receiving connection pad, and a second receiving connection pad that interconnect with said second electrical circuitry using said metal conductors, said integrating providing an electrical connection between said first electrical circuitry and said second electrical circuitry wherein said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad;

crossing said carrier substrate over at least one of said metal conductors on said receiving substrate; and

configuring said carrier substrate to be at least five times larger in feature size than said first object and at least five times smaller in feature size than said receiving substrate.

32. A method of making an electronic assembly comprising:

creating and separating a first object from a host substrate, said first object having a first electrical circuitry therein;

depositing said first object into a recessed region in a carrier substrate, said first object being recessed below a surface of said carrier substrate, said carrier further comprising a first carrier connection pad and a second carrier connection pad that forms a first interconnection with said first object using metal conductors;

integrating said carrier substrate to a receiving substrate including a second electrical circuitry which is substantially planar, said receiving substrate further including a first receiving connection pad, and a second receiving connection pad that forms a second interconnection with said second electrical circuitry using said metal conductors, said integrating providing an electrical connection between said first electrical circuitry and said second electrical circuitry wherein said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad; and

configuring said first object, said carrier substrate, said receiving substrate, said first interconnection, said second interconnection, and said electrical interconnection to be essentially coplanar.

33. An electronic assembly comprising:

a first object created and separated from a host, said first object having a first electrical circuitry therein;

a carrier substrate said first object deposited in a recessed region provided in said carrier substrate through a fluidic self-assembly process, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that interconnect with said first object using metal connectors, said first object further being recessed below a surface of said carrier substrate; and

a receiving substrate including a second electrical circuitry which is substantially planar, said receiving substrate further including a first receiving connection pad, and a second receiving connection pad that interconnect with said second electrical circuitry using said metal connectors, said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad providing an electrical connection between said first electrical circuitry and said second electrical circuitry.

34. An electronic assembly as in claim 33 wherein said carrier substrate is flexible.

35. A method of making an electronic assembly comprising:

creating and separating a first object from a host substrate, said first object having a first electrical circuitry therein;

using a fluidic self-assembly process to deposit said first object into a complimentary recessed region provided in a carrier substrate, said carrier substrate further comprising a first carrier connection pad and a second carrier connection pad that interconnect with said first object using metal conductors, said first object further being recessed below a surface of said carrier substrate; and

integrating said carrier substrate to a receiving substrate including a second electrical circuitry which is substantially planar and including a first receiving connection pad, and a second receiving connection pad that interconnect with said second electrical circuitry using said metal conductors, said integrating providing an electrical connection between said first electrical circuitry and said second electrical circuitry wherein said first receiving connection pad couples to said first carrier connection pad and said second receiving connection pad couples to said second carrier connection pad.

36. A display device comprising:

an array of display drivers, each of said display drivers is formed in a host substrate and then removed from said host substrate and then deposited onto a carrier substrate such that each of said display drivers is recessed below a surface of said carrier substrate;

said carrier substrate further including a plurality of carrier connection pads, said plurality of carrier connection pads interconnecting with said array of display drivers and coupling to a receiving substrate;

said receiving substrate including an array of pixel electrodes interconnecting to a plurality of receiving connection pads wherein said plurality of receiving connection pads couples to said plurality of carrier connection pads providing necessary electrical connections between said array of display drivers and said array of pixel electrodes; and

said array of display drivers control said display device.

37. A display device as in claim 36 wherein said display drivers drive pixel electrodes which control a display medium which comprises one of a liquid crystal material, an electrophoretic material, an organic light emitting diode material, a semiconductor light emitting diode material, particle-based material, thin film electroluminescent material, and electrochromic material.

38. A display device as in claim 36 wherein said display device is a multi-feature-size structure in which said carrier substrate is at least five times larger in feature size than each of said display drivers and wherein said carrier substrate is at least five times smaller in feature size than said receiving substrate.

39. A display device as in claim 36 wherein said carrier substrate is at least ten times larger than said display drivers and said carrier substrate is at least ten times smaller than said receiving substrate.

40. A display device as in claim 36 wherein said plurality of carrier connection pads and said plurality of receiving connection pads are interconnected by conductive adhesives.

41. A display device as in claim 36 wherein each of said driver displays are integrated circuits designed to drive said array of pixel electrodes.

42. A display device as in claim 36 wherein said carrier substrate crosses over at least one electrical connection on said receiving substrate.

43. A display device as in claim 36 wherein each of said display drivers is deposited onto said carrier substrate through a fluidic self-assembly process.

44. A display device as in claim 36 wherein said carrier substrate is flexible.

45. A method of making a display device comprising:

forming an array of display drivers, each of said display drivers being formed in a host substrate;

removing said array of display drivers from said host substrate;

depositing said array of display drivers onto a carrier substrate such that each of said display drivers is recessed below a surface of said carrier substrate, said carrier substrate further including a plurality of carrier connection pads which interconnect with said array of display drivers;

integrating said display drivers to said array of display driver to a receiving substrate which includes an array of pixel electrodes and a plurality of receiving connection pads which interconnect with said array of pixel electrodes, said integrating providing necessary electrical connections between said array of display drivers and said array of pixel electrodes and occurring when said plurality of carrier connection pads couples to said plurality of receiving connection pads; and

designing said array of display drivers to control said display device.

46. A method of making a display device as in claim 45 further comprising configuring said display drivers to drive pixel electrodes which control a display medium which comprises one of a liquid crystal material, an electrophoretic material, an organic light emitting diode material, a semiconductor light emitting diode material, particle-based material, thin film electroluminescent material, and electrochromic material.

47. A method of making a display device as in claim 45 further comprising configuring said display device to be a multi-feature-size structure in which said carrier substrate is at least five times larger in feature size than each of said display drivers and wherein said carrier substrate is at least five times smaller in feature size than said receiving substrate.

48. A method of making a display device as in claim 45 further comprising configuring said carrier substrate to be at least ten times larger than said display drivers and said carrier substrate to be at least ten times smaller than said receiving substrate.

49. A method of making a display device as in claim 45 comprising insulating said arrays of pixel electrodes from said display medium with an insulation layer.

50. A method of making a display device as in claim 45 wherein a fluidic self-assembly process is used to couple each of said array of display drivers onto said carrier substrate.

51. A method of making a display device as in claim 45 further comprising configuring said carrier substrate to be flexible.