Erase verify for non-volatile memory

• US 20050270860A1
• Filed: 08/05/2005
• Published: 12/08/2005
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Granted Patent: US 7,236,400 B2
• Time in Patent Office: Days
• US Class Current: 365/189.50
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

Claims

1. A non-volatile memory comprising:

an array of non-volatile memory cells arranged in columns using bit lines;

a verify circuit selectively coupled to the bit lines to determine if the memory cells have an erase level that is within an erase level window defined by first and second reference signals; and

a current-to-voltage converter coupled between a selected one of the bit lines and the verify circuit, the current-to-voltage converter comprising;

a resistor; and

an activation circuit having an input coupled to the resistor and an output coupled to the verify circuit.

2. The non-volatile memory of claim 1 wherein the memory cells comprise a plurality of floating gate memory cells.

3. The non-volatile memory of claim 1 wherein each memory cell is comprised of a source region, a drain region, and a control gate.

4. The non-volatile memory of claim 3 wherein the control gate of each memory cell in a row of the array is coupled by a word line.

5. The non-volatile memory of claim 3 wherein the drain regions of each memory cell in a column are coupled by a common bit line.

6. The non-volatile memory of claim 3 wherein the source regions of each memory cell in a column are coupled by a common source line.

7. The non-volatile memory of claim 1 wherein the current-to-voltage converter converts a bit line current to a bit line voltage that indicates a state of the memory cell.

8. A bit line verify system comprising:

an array of non-volatile memory cells arranged in columns using bit lines;

a verify circuit selectively coupled to the bit lines and generating an output signal indicative of the memory cells having an erase level defined by a bit line voltage that is within an erase level window defined by first and second reference voltages;

a current-to-voltage converter coupled between a selected one of the bit lines and the verify circuit to generate the bit line voltage in response to a bit line current, the converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor; and

an inverter circuit coupled between a gate of the activation transistor and a drain of the activation transistor, wherein the source of the activation transistor is further coupled to the verify circuit; and

control circuitry to perform erase operations in response to the output signal.

9. The system of claim 8 and further comprising first and second reference current circuits coupled to the verify circuit to respectively provide the first and second reference currents.

10. The system of claim 8 and further comprising first and second current sources coupled to the verify circuit to respectively provide the first and second reference current.

11. The system of claim 10 wherein the first current source comprises a floating gate transistor programmed to conduct a specific amount of current in response to a control signal.

12. The system of claim 8 wherein the memory cells comprise a plurality of floating gate memory cells.

13. A memory device with an erase verify system, the device comprising:

a memory array having a plurality of memory cells coupled to a bit line;

a verify circuit for selectively comparing a bit line voltage with a first and second reference voltage and generating a first and a second output signal in response to the respective comparisons;

a first current-to-voltage converter coupled between a selected one of the bit lines and the verify circuit to generate the bit line voltage in response to a bit line current, the first current-to-voltage converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor; and

an inverter circuit coupled between a gate of the activation transistor and a drain of the activation transistor, wherein the source of the activation transistor is further coupled to the verify circuit; and

control circuitry to perform erase operations in response to the first and second output signals.

14. The memory device of claim 13 and further comprising:

a reference current circuit for generating a reference current; and

a second current-to-voltage converter coupled between the reference current circuit and the verify circuit, wherein the second current-to-voltage converter provides the first and second reference voltages from the reference current.

15. The memory device of claim 13 wherein the plurality of memory cells comprise a plurality of flash memory cells.

16. A memory system comprising:

a processor for controlling the system; and

a memory device coupled to the processor and comprising;

a memory array having a plurality of memory cells coupled to a bit line;

a verify circuit for selectively comparing a bit line voltage with a first and second reference voltage and generating a first and a second output signal in response to the respective comparisons;

a current-to-voltage converter coupled between a selected one of the bit lines and the verify circuit to generate the bit line voltage in response to a bit line current, the current-to-voltage converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor; and

an inverter circuit coupled between a gate of the activation transistor and a drain of the activation transistor, wherein the source of the activation transistor is further coupled to the verify circuit; and

control circuitry to perform erase operations in response to the first and second output signals.

17. The system of claim 16 wherein the control circuitry is coupled to control lines from the processor.

18. The system of claim 16 wherein the processor generates data and address lines for communicating with the memory device.

19. The system of claim 16 wherein the memory array is comprised of flash memory cells.

20. A memory device with an erase verify system, the device comprising:

a memory array having a plurality of memory cells coupled to a bit line that has a bit line current indicative of a state of a memory cell;

a first comparator to compare a bit line voltage with a first reference voltage and produce a first output signal;

a second comparator to compare the bit line voltage with a second reference voltage and produce a second output signal;

a current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to the bit line current, the current-to-voltage converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor; and

an inverter circuit coupled between a gate of the activation transistor and a drain of the activation transistor, wherein the source of the activation transistor is further coupled to the verify circuit; and

control circuitry to perform erase operations in response to the first and second output signals.