RF isolator with differential input/output

• US 20050271148A1
• Filed: 12/22/2004
• Published: 12/08/2005
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Dupuis, Timothy
• Granted Patent: US 7,376,212 B2
• Time in Patent Office: Days
• US Class Current: 375/258
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A system for providing voltage isolation includes the first and second chips, each containing functional circuitry. The chips are interconnected via at least one RF isolation link that provides voltage isolation between the first chip and the second chip and limits common mode signals therebetween.

Claims

1. A system comprising:

a first chip containing functional circuitry;

a second chip containing functional circuitry; and

at least one RF isolation link interconnecting the first and the second chip, the RF isolation link providing voltage isolation between the first chip and the second chip and limiting common mode signals passing through the at least one RF isolation link.

2. The system of claim 1, wherein the at least one RF isolation link is integrated on the first chip and the second chip.

3. The system of claim 1, wherein the RF isolation link further comprises:

a first transformer on the first chip;

a second center tap transformer on the second chip;

a transmitter associated with the first transformer for transmitting an RF carrier onto the RF isolation link;

a receiver associated with the second center tap transformer for receiving an RF carrier onto the RF isolation link.

4. The system of claim 3, wherein the power supply voltage of the transmitter and the receiver varies with respect to temperature.

5. The system of claim 3, wherein the power supply voltage of the transmitter and the receiver varies with respect to process.

6. The system of claim 3 wherein the first transformer is a center tap transformer.

7. The system of claim 1, wherein the RF isolation link further comprises:

a first transformer on the first chip;

a second center tap transformer on the second chip;

first transceiver circuitry associated with the first transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link;

second transceiver circuitry associated with the second center tap transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link.

8. The system of claim 1, wherein the at least one RF isolation link further comprises:

a transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output;

a first transformer for electromagnetically coupling the transmitter output on to a link;

a second center-tap transformer for electromagnetically coupling the transmitter output on the link to the amplifier inputs;

a differential amplifier for amplifying signals applied to inputs of the differential amplifier;

a detector coupled to the output of the differential amplifier for detecting the presence or absence of the RF carrier signal in an amplified transmitter output from the amplifier stage.

9. The system of claim 8, wherein the transmitter outputs the RF carrier as the transmitter output responsive to a logical “

1”

logical data signal.

10. The system of claim 8 wherein the transmitter shuts down the RF carrier as the transmitter output responsive to a logical “

0”

logical data signal.

11. The system of claim 8, wherein the presence of the RF carrier signal indicates a received logical “

1” and

the absence of the RF carrier signal indicates a logical “

0”

.

12. The system of claim 1, wherein the at least one RF isolation link transmits data between the first and the second chip using amplitude modulation.

13. The system of claim 1, wherein the at least one RF isolation link transmits data between the first and the second chip using frequency modulation.

14. An apparatus comprising:

a chip containing functional circuitry; and

a portion of at least one RF isolation link interconnecting the chip with an external chip, the RF isolation link providing voltage isolation between the chip and the external chip and limiting common mode signals passing through the portion of at least one RF isolation link.

15. The apparatus of claim 14, wherein the portion of the at least one RF isolation link comprises:

a transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output; and

an integrated center-tap transformer for electromagnetically coupling the transmitter output onto an external link.

16. The apparatus of claim 14, wherein the portion of the at least one RF isolation link comprises:

a receiver for detecting the presence or absence of an RF carrier signal in a signal on an external link; and

an integrated center-tap transformer for electromagnetically coupling the signal on the external link to the receiver.

17. The apparatus of claim 16, wherein the receiver further comprises:

a differential amplifier for amplifying the signal on the external link;

a detector coupled to the differential amplifier for detecting the presence or absence of the RF carrier signal in an amplified transmitter output from the amplifier stage.

18. A circuit package, comprising:

a first die containing functional circuitry;

a second die containing functional circuitry; and

at least one RF isolation link interconnecting the first and the second die, the RF isolation link providing voltage isolation and limiting common mode signals between the first die and the second die.

19. The system of claim 18, wherein the RF isolation link further comprises:

a first transformer on the first die;

a second center-tap transformer on the second die;

a transmitter associated with the first transformer for transmitting an RF carrier onto the RF isolation link;

a receiver associated with the second transformer for receiving an RF carrier onto the RF isolation link.

20. The system of claim 18, wherein the RF isolation link further comprises:

a first transformer on the first chip;

a second transformer on the second chip;

first center-tap transceiver circuitry associated with the first transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link;

second transceiver circuitry associated with the second transformer for transmitting and receiving an RF carrier onto the at least one RF isolation link.

21. The system of claim 18, wherein the at least one RF isolation link further comprises:

a transmitter responsive to a logical data signal and an RF carrier signal for generating a transmitter output;

a first transformer for electromagnetically coupling the transmitter output on to a link;

a differential amplifier for amplifying signals applied to inputs of the differential amplifier;

a second center-tap transformer for electromagnetically coupling the transmitter to the amplifier stage input;

a detector coupled to the differential amplifier for detecting the presence or absence of the RF carrier signal in an amplified transmitter output from the amplifier stage.