Method for establishing a communication link

• US 20050271177A1
• Filed: 08/17/2005
• Published: 12/08/2005
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Demir, Alpaslan, Grieco, Donald M.
• Granted Patent: US 7,433,437 B2
• Time in Patent Office: Days
• US Class Current: 375/362
• CPC Class Codes: H04B 1/7083 Cell search, e.g. using a three-step approach
• CPC Class Codes: H04J 11/0069 Cell search, i.e. determining cell identity [cell-ID] design of multiplexing codes H04J13/00; processing access restriction or access information H04W48/16; discovery of network devices for network data management H04W8/005; sounding signals for channel estimation H04L25/0226; structure of reference signals in multicarrier modulation systems H04L27/2613; frame, time or carrier synchronisation in multicarrier modulation systems H04L27/2655
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04W 48/16 Discovering, processing access restriction or access information
• CPC Class Codes: H04W 56/00 Synchronisation arrangements

Abstract

A user equipment (UE) for establishing a communication link comprising a first module for processing a received communication signal and generating an index value associated with a primary synchronization code within said communication signal; a second module for generating a scrambling code group number, a slot offset, and secondary synchronization code based on output provided by the first module; a third module for retrieving a primary scrambling code based on the scrambling code group number and slot offset; and a controller coupled to said first module, second module, and third module for controlling an a search frequency of the UE for establishing a communication link.

Claims

1. A user equipment (UE) for establishing a communication link comprising:

a first module for processing a received communication signal and generating an index value associated with a primary synchronization code within said communication signal, said first module comprising;

a splitter for splitting a sampled communication signal into even and odd samples;

a Hierarchical Golay Correlator (HGC) for correlating the even and odd samples with a primary synchronization code of the communication signal, and for generating complex values of the even and odd samples;

an absolute value modifier (AVM) for approximating signal strength values for each of the even and odd samples;

a decision circuit for accumulating the approximate signal strength values of the samples within a frame of the communication signal, assigning as an index value a highest accumulated signal strength value, and for determining a chip offset based on said index value;

a normalizer circuit for normalizing the accumulated signal strength value;

a look-up table for determining a gain factor;

a multiplier for generating a noise threshold based on the normalized signal strength value and on the gain factor; and

a comparator for comparing the noise threshold to the index value in order to make a first decision;

a second module for generating a scrambling code group number, a slot offset, and secondary synchronization code based on output provided by the first module;

a third module for retrieving a primary scrambling code based on the scrambling code group number and slot offset; and

a controller coupled to said first module, second module, and third module for controlling a search frequency of the UE for establishing a communication link.

2. The UE of claim 1, wherein the second module comprises:

a delay module for delaying the chip offset determined in the first module until the first module makes the first decision;

a sample selector for extracting a peak HGC output;

a conjugator for conjugating the extracted peak HGC output;

an envelope remover for removing an envelope sequence from the received communication signal;

a Fast Hadamard Transformer (FHT) for transforming a Hadamard matrix of the communication signal;

a complex multiplier for phase correcting the transformed Hadamard matrix using the conjugated peak HGC output;

an input matrix generator for generating an input matrix comprising real parts of the Hadamard matrix output by the multiplier;

a decision circuit for generating a correlation matrix comprising the scrambling code group number and the slot offset;

an RS encoder; and

a comparator for comparing a maximum entry in the correlation matrix to a threshold for outputting a decision.

3. The UE of claim 1, wherein the third module comprises:

a plurality of scrambling code generators, each for retrieving the code group number generated by the second module and for generating a scrambling code therefrom;

a plurality of correlator circuits, for generating and accumulating correlations of data symbols of the communication signal using output from the scrambling code generators;

a noise estimator;

a decision circuit for generating the primary scrambling code based on output from the correlator circuits;

a decision support circuit for outputting the primary scrambling code to the controller;

a multiplier for calculating a threshold value by multiplying noise estimates output from the noise estimator by a gain value; and

a comparator for comparing the calculated threshold value to a maximum correlation value and for generating a decision therefrom.

4. A method of generating an index value associated with a primary synchronization code within a communication signal, said method comprising:

splitting a sampled communication signal into even and odd samples;

correlating the even and odd samples with a primary synchronization code of the communication signal;

generating complex values of the even and odd samples;

approximating signal strength values for the even and odd samples;

accumulating the approximate signal strength values within a frame of the communication signal; and

assigning as an index value a highest accumulated signal strength value.