Please download the dossier by clicking on the dossier button x
×

Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique

  • US 20050272208A1
  • Filed: 08/16/2005
  • Published: 12/08/2005
  • Est. Priority Date: 05/03/2002
  • Status: Abandoned Application
First Claim
Patent Images

1. A method for manufacturing a power mosfet comprising the steps of:

  • forming a gate trench mask with open and closed regions on the surface of a semiconductor substrate;

    removing semiconductor material from areas exposed by the open regions of the trench mask to form a plurality of gate trenches;

    forming a sacrificial gate oxide layer on the sidewalls of the trenches;

    implanting the substrate with a drift region implant that penetrates the oxide on the floors of the trenches and is stopped on the surface of the substrate by the residual trench mask;

    diffusing the drift region implant to form a continuous drift layer and define the length of the gate and to form a continuous lightly doped drift region extending between sidewalls of the trenches and from the drain layer toward the source region and along a lower portion of the trench sidewalls to provide a variable, lightly doped concentration that gradually decreases in density from the sidewalls of the trenches toward a plane about midway between the trenches;

    removing the trench mask and the sacrificial oxide and forming a gate oxide on the surface of the trench;

    depositing a layer of polysilicon on the surface of the substrate and in the trenches;

    removing the polysilicon from the surface of the semiconductor substrate and leaving enough polysilicon in the gate trenches to form gates in the trenches;

    implanting the substrate with a source dopant to form source regions in the surface of the semiconductor substrate and to increase the conductivity of the polysilicon in the trenches to form gate regions in the trenches;

    depositing a layer of BPSG on the substrate;

    removing at least apart of the BPSG layer to expose portions of the surface having the source implant;

    depositing and patterning a conductive layer over the surface of the substrate to form electrical contacts to the source regions.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×