Method of manufacturing metal-oxide-semiconductor transistor

• US 20050272213A1
• Filed: 06/07/2005
• Published: 12/08/2005
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Chin-Cheng Chien, Hsiang-Ying Wang, Neng-Hui Yang, Yu-Ren Wang
• Original Assignee: Chin-Cheng Chien, Hsiang-Ying Wang, Neng-Hui Yang, Yu-Ren Wang
• Inventors: Chien, Chin-Cheng, Wang, Hsiang-Ying, Yang, Neng-Hui, Wang, Yu-Ren
• Granted Patent: US 7,435,658 B2
• Time in Patent Office: Days
• US Class Current: 438/303
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence

Abstract

A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

Claims

1. A method of manufacturing a metal-oxide-semiconductor (MOS) transistor, comprising the steps of:

providing a substrate having a gate structure thereon;

forming a first spacer on the sidewall of the gate structure;

performing a pre-amorphization implantation to amorphize a portion of the substrate;

forming a doped source/drain extension region in the substrate on each side of the first spacer;

forming a second spacer on the sidewall of the first spacer;

forming a doped source/drain region in the substrate on each side of the second spacer;

performing a solid phase epitaxial process to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal; and

performing a post-annealing process, wherein the annealing temperature in the post-annealing operation is higher than the operating temperature in the solid phase epitaxial process.

2. The method of claim 1, wherein the post-annealing operation comprises performing a rapid thermal annealing process.

3. The method of claim 1, wherein the post-annealing process comprises heating the substrate to an annealing temperature of about 850°

C.

4. The method of claim 3, wherein the post-annealing process comprises maintaining the substrate at the annealing temperature for a period of about 20 seconds.

5. The method of claim 1, wherein the post-annealing process comprises heating the substrate to an annealing temperature between about 900°

C. to 1000°

C.

6. The method of claim 5, wherein the post-annealing process comprises maintaining the substrate at the annealing temperature for a spike period.