Method and apparatus to avoid incoherency between a cache memory and flash memory

• US 20050273560A1
• Filed: 06/03/2004
• Published: 12/08/2005
• Est. Priority Date: 06/03/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gould, Geoffrey A., Edgington, Michael L., Hulbert, Jared E.
• Application Number:
  US10/861,266
• Publication Number:
  US 20050273560A1
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

Briefly, in accordance with an embodiment of the invention, a method and apparatus to avoid incoherency between a cache memory and a flash memory is provided. The method may include invalidating at least one cache line of information stored in the cache memory to avoid incoherency between the cache memory and the flash memory in response to a flash erase operation, a flash write operation, an operation that makes information inaccessible in the flash memory, or an operation that moves information from one region of the flash memory to another region of the flash memory. Other embodiments are described and claimed.

Claims

1. A method, comprising:

invalidating at least one cache line of information stored in a cache memory in response to a flash write operation or a flash erase operation to avoid incoherency between the cache memory and a flash memory.

2. The method of claim 1, wherein invalidating comprises invalidating all information stored in the cache memory in response to the flash write operation or the flash erase operation to avoid incoherency between the cache memory and the flash memory.

3. The method of claim 1, wherein the at least one cache line of information includes a copy of dynamic information stored at an address in the flash memory and wherein invalidating comprises invalidating the at least one cache line of information in response to the flash write operation or the flash erase operation that alters the dynamic information stored at the address in the flash memory.

4. The method of claim 1, wherein invalidating comprises invalidating all cache lines stored in the cache memory affected by the flash erase operation or the flash write operation.

5. The method of claim 1, wherein invalidating comprises invalidating all cache lines stored in the cache memory that have information that correspond to information stored in the flash memory at the address range that is being written to, or erased in the flash memory.

6. The method of claim 1, further comprising reading information from the flash memory using a synchronous burst read operation, wherein reading comprises transferring information from the flash memory to the cache memory using a synchronous burst read operation.

7. A method to avoid incoherency between the cache memory and the flash memory, comprising:

invalidating at least one cache line of information stored in the cache memory in response to an operation that makes information inaccessible in the flash memory.

8. The method of claim 7, wherein the operation that makes information inaccessible comprises locking a section of the flash memory to prevent read-access to information stored in the section.

9. The method of claim 7, wherein the at least one cache line of information corresponds to information stored at a particular address in the flash memory and wherein invalidating comprises invalidating the at least one cache line of information in response to an operation that makes the information stored at the particular address in the flash memory inaccessible using a flash read operation.

10. A method to avoid incoherency between a cache memory and a flash memory, comprising:

invalidating at least one cache line of information stored in the cache memory in response to moving information from a first region of a flash memory to a second region of the flash memory.

11. The method of claim 10, wherein invalidating comprises invalidating all cache lines that have a copy of information stored in the first region of the flash memory.

12. The method of claim 10, wherein the at least one cache line of information includes a copy of information stored in the first region of the flash memory and wherein invalidating comprises invalidating the at least one cache line of information in response to an operation that moves the information stored in the first region of the flash memory to the second region of the flash memory to improve wear leveling in the flash memory.

13. An article comprising a storage medium having stored thereon instructions, that, when executed by a computing platform, result in:

invalidating at least one cache line of information stored in a cache memory to avoid incoherency between the cache memory and a flash memory in response to a flash erase operation, a flash write operation, an operation that makes information inaccessible in the flash memory, or an operation that moves information from one region of the flash memory to another region of the flash memory.

14. The article of claim 13, wherein the instructions, when executed, further result in:

reading information from the flash memory using a synchronous burst read operation, wherein reading comprises transferring information from the flash memory to the cache memory using a synchronous burst read operation.

15. The article of claim 13, wherein the operation that makes information inaccessible comprises locking a section of the flash memory to prevent read-access to information stored in the section.

16. An apparatus, comprising:

a cache memory; and

a controller adapted to invalidate at least one cache line of information stored in the cache memory to avoid incoherency between the cache memory and a flash memory in response to a flash erase operation, a flash write operation, an operation that makes information inaccessible in a flash memory, or an operation that moves information from one region of the flash memory to another region of the flash memory.

17. The apparatus of claim 16, further comprising a central processing unit (CPU) core coupled to the controller.

18. The apparatus of claim 16, wherein the cache memory comprises:

an instruction cache coupled to the controller; and

a data cache coupled to the controller.

19. A system, comprising:

an antenna; and

a processor coupled to the antenna, wherein the processor comprises;

a cache memory and

a controller adapted to invalidate at least one cache line of information stored in the cache memory to avoid incoherency between the cache memory and a flash memory in response to a flash erase operation, a flash write operation, an operation that makes information inaccessible in a flash memory, or an operation that moves information from one region of the flash memory to another region of the flash memory.

20. The system of claim 19, wherein the processor further comprises a central processing unit (CPU) core coupled to the controller.

21. The system of claim 19, wherein the system is a wireless phone.

22. A method, comprising:

copying alterable information from a flash memory to a cache memory.

23. The method of claim 22, wherein the alterable information is alterable data or alterable code.

24. The method of claim 23, wherein the alterable code is operating system (O/S) code or a software application.

25. The method of claim 23, wherein the alterable data is a java applet, ring tone data, or telephone number data.

26. The method of claim 22, further comprising copying the alterable information from the cache memory to a central processing unit (CPU) core.

27. The method of claim 22, wherein the cache memory is an instruction cache memory.

28. The method of claim 22, wherein the cache memory is a data cache memory.

29. The method of claim 22, further comprising:

writing information to a location in the flash memory; and

invalidating at least one cache line of information stored in the cache memory in response to the writing of information to the location in the flash memory to avoid incoherency between the cache memory and the flash memory, wherein the at least one cache line of information includes a copy of alterable flash information stored at the location in the flash memory that is being written to during the writing.

30. The method of claim 22, further comprising:

erasing information at a location in the flash memory; and

invalidating at least one cache line of information stored in a cache memory in response to the erasing of information in the flash memory to avoid incoherency between the cache memory and the flash memory, wherein the at least one cache line of information includes a copy of alterable flash information that is stored at the location in the flash memory that is being erased by the erasing.

31. A method to avoid incoherency between a cache memory and a nonvolatile memory, comprising:

invalidating at least one cache line of information stored in the cache memory in response to a write operation to the nonvolatile memory, an erase operation to the nonvolatile memory, an operation that makes information inaccessible in the nonvolatile memory, or an operation that moves information from one region of the nonvolatile memory to another region of the nonvolatile memory, wherein the nonvolatile memory is a nonvolatile memory other than a disk memory.

32. The method of claim 31, wherein the nonvolatile memory is a polymer memory.