Method and system for generating clocks for standby mode operation in a mobile communication device

• US 20050273637A1
• Filed: 09/01/2004
• Published: 12/08/2005
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lu, Paul
• Granted Patent: US 7,496,774 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.

Claims

1. A method for reducing power while in standby mode, the method comprising:

monitoring for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode;

upon receiving said at least one event, enabling at least one of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal.

2. The method according to claim 1, further comprising determining an identity of said at least one received event.

3. The method according to claim 1, further comprising if said at least one of said first clock signal and said second clock signal is enabled, disabling said at least one of said first and said second clock signal.

4. The method according to claim 1, further comprising, responsive to receiving at least one event requiring a transition back to the standby mode, transitioning back to the standby mode utilizing said low power standby clock signal while in the standby mode.

5. The method according to claim 1, further comprising consuming said at least one of said first clock signal and said second clock signal by at least one processing device.

6. The method according to claim 5, wherein said at least one processing device is a main processor.

7. The method according to claim 1, further comprising generating said at least one of said first clock signal by an off-chip clock source.

8. The method according to claim 7, wherein said off-chip clock source has a higher frequency and a greater accuracy than said low power standby clock signal.

9. The method according to claim 1, further comprising generating said at least one of a second clock signal by an on-chip clock source.

10. The method according to claim 9, wherein said on-chip clock source is a main phase lock loop.

11. A machine-readable storage having stored thereon, a computer program having at least one code section for reducing power while in standby mode, the at least one code section executable by a machine for causing the machine to perform steps comprising:

monitoring for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode;

upon receiving said at least one event, enabling at least one of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal.

12. The machine-readable storage according to claim 11, further comprising determining an identity of said at least one received event.

13. The machine-readable storage according to claim 11, further comprising if said at least one of said first clock signal and said second clock signal is enabled, disabling said at least one of said first and said second clock signal.

14. The machine-readable storage according to claim 11, further comprising, responsive to receiving at least one event requiring a transition back to the standby mode, transitioning back to the standby mode utilizing said low power standby clock signal while in the standby mode.

15. The machine-readable storage according to claim 11, further comprising consuming said at least one of said first clock signal and said second clock signal by at least one processing device.

16. The machine-readable storage according to claim 15, wherein said at least one processing device is a main processor.

17. The machine-readable storage according to claim 11, further comprising generating said at least one of said first clock signal by an off-chip clock source.

18. The machine-readable storage according to claim 17, wherein said off-chip clock source has a higher frequency and a greater accuracy than said low power standby clock signal.

19. The machine-readable storage according to claim 11, further comprising generating said at least one of a second clock signal by an on-chip clock source.

20. The machine-readable storage according to claim 19, wherein said on-chip clock source is a main phase lock loop.

21. A system for reducing power while in standby mode, the system comprising:

at least one processor that monitors for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode;

upon receiving said at least one event, said at least one processor enables at least one of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal.

22. The system according to claim 21, wherein said at least on processor determines an identity of said at least one received event.

23. The system according to claim 21, wherein said at least one processor disables said at least one of said first and said second clock signal, if said at least one of said first clock signal and said second clock signal is enabled.

24. The system according to claim 21, wherein, responsive to receiving at least one event requiring a transition back to the standby mode, wherein said at least one processor transitions back to the standby mode utilizing said low power standby clock signal while in the standby mode.

25. The system according to claim 21, wherein said at least one processor consumes said at least one of said first clock signal and said second clock signal by at least one processing device.

26. The system according to claim 25, wherein said at least one processing device is a main processor.

27. The system according to claim 21, further comprising an off-chip clock source that generates said at least one of said first clock signal.

28. The system according to claim 27, wherein said off-chip clock source has a higher frequency and a greater accuracy than said low power standby clock signal.

29. The system according to claim 21, further comprising an on-chip clock source that generates said at least one of a second clock signal.

30. The system according to claim 29, wherein said on-chip clock source is a main phase lock loop.