Deep trench super switch device

• US 20050275016A1
• Filed: 06/01/2005
• Published: 12/15/2005
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Qu, Zhijun
• Granted Patent: US 7,268,395 B2
• Time in Patent Office: Days
• US Class Current: 257/342
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonconductive material.

Claims

1. A deep trench super switch device comprising:

a drain electrode;

a body formed on the drain electrode of a first conductivity type;

an epitaxial layer of a first conductivity type formed on the body of the first conductivity type;

a plurality of trenches etched into the epitaxial layer, each of the plurality of trenches containing a stack of conductive floating polysilicon layers, a gate electrode on top of the stack of conductive floating polysilicon layers, and a nonconductive material surrounding each of the gate electrode and the conductive polysilicon layers;

a plurality of channel regions of a second conductivity type, each of the channel regions being formed on the epitaxial layer and between two adjacent trenches;

a plurality of source regions of the first conductivity type, each of the source regions being formed in one of the channel regions; and

a plurality of source contacts, each of the source contacts contacting one of the source regions and one of the channel regions.

2. The deep trench super switch device of claim 1, wherein the plurality of trenches are arranged parallel to one another.

3. The deep trench super switch device of claim 1, wherein the plurality of trenches extend for the entire depth of the epitaxial layer.

4. The deep trench super switch device of claim 1, wherein the nonconductive material is silicon dioxide.

5. The deep trench super switch device of claim 1, wherein the plurality of trenches do not extend for the entire depth of the epitaxial layer.

6. The deep trench super switch device of claim 1, wherein the gate electrode is a conductive polysilicon layer.

7. A process for forming a deep trench super switch device comprising the following steps:

forming a body of a first conductivity type;

forming an epitaxial layer of the first conductivity type on the body;

forming a drain electrode on the bottom of the body;

etching a plurality of trenches in the epitaxial layer;

placing a stack of conductive floating polysilicon layers, and nonconductive material, surrounding the stack of conductive floating polysilicon layers, in each of the plurality of trenches;

forming a plurality of channel regions of a second conductivity type, each of the plurality of channel regions being formed on the epitaxial layer and between two adjacent trenches of the plurality of trenches;

forming a plurality of source regions of the first conductivity type, each of the source regions being formed in one of the channel regions;

forming a plurality of source contacts, each of the plurality of source contacts contacting one of the source regions and one of the channel regions; and

forming a plurality of gate electrodes, each gate electrode being formed in a trench of the plurality of trenches, each gate electrode being surrounded by the nonconductive material.

8. The process of claim 7, wherein the plurality of trenches are arranged parallel to one another.

9. The process of claim 7, wherein the plurality of trenches extend for the entire depth of the epitaxial layer.

10. The process of claim 7, wherein the plurality of trenches do not extend for the entire depth of the epitaxial layer.

11. The process of claim 7, wherein the nonconductive material is silicon dioxide.

12. The process of claim 7, wherein the gate electrode is a conductive polysilicon layer.