Gate Electrode Architecture for Improved Work Function Tuning and Method of Manufacture

• US 20050275035A1
• Filed: 06/09/2005
• Published: 12/15/2005
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: Agency For Science Technology and Research
• Original Assignee: Agency For Science Technology and Research
• Inventors: Balasubramanian, Narayanan, Bera, Lakshmi Kanta, Mathew, Shajan
• Granted Patent: US 7,397,090 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.

Claims

1. A method for fabricating a first gate electrode having a first working function and a second gate electrode having a second working function, the method comprising:

forming a first well of a first conductivity type and a second well of a second conductivity type;

depositing a gate dielectric layer over at least a portion of the first and second wells;

forming a multi-layer stack over the dielectric layer which extends over the first well, the multi-layer stack comprising two or more thin metal/metal nitride layers;

depositing a thick metal/metal nitride layer over (i) the multi-layer stack to form the first gate electrode, and (ii) the gate dielectric layer portion which extends over the second well to form the second gate electrode; and

annealing the first and second gate electrodes.

2. The method of claim 1, further comprising removing the multi-layer stack from the area of the second well.

3. The method of claim 1, wherein annealing the first and second gate electrodes comprises thermal annealing.

4. The method of claim 1, wherein the thin metal/metal nitride layers comprises a metal or metal nitride from the group consisting of Ti, Ta, Hf, Nb, Mo, Zr, and W and their nitrides.

5. The method of claim 1, wherein the thick metal/metal nitride comprises a metal/metal nitride from the group consisting of Ti, Ta, Hf, Nb, Mo, Zr and W and their nitrides.

6. The method of claim 1, wherein the multi-stack comprises three thin metal/metal nitride layers.

7. The method of claim 1, wherein the gate dielectric layer comprises material from the group consisting of silicon dioxide, silicon nitride, oxynitride, silicate, hafnium oxide, aluminum oxide, BST, and tantalum pentoxide.

8. A semiconductor device having a first well of a first conductivity type and a second well of a second conductivity type, the semiconductor device comprising:

a gate dielectric layer extending over at least a portion of the first well and the second well;

a first gate electrode disposed on the gate dielectric layer and extending over the first well, the first gate electrode comprising a multi-layer stack, comprising;

(i) a first thin metal/metal nitride layer disposed on the gate dielectric layer;

(ii) a second thin metal/metal nitride layer disposed on the first thin metal/metal nitride layer;

(iii) a third thin metal/metal nitride layer disposed on the second thin metal/metal nitride layer; and

(iv) a first thick metal/metal nitride layer disposed on the third thin metal/metal nitride layer

a first source electrode and a first drain electrode formed in the first well adjacent to the first gate electrode;

a second gate electrode disposed on the gate dielectric layer and extending over the second well, the second gate electrode comprising a portion of the first thick metal/metal nitride layer; and

a second source electrode and a second drain electrode formed in the second well adjacent to the second gate electrode.

9. The semiconductor device of claim 8, wherein, after annealing, the multi-layer stack comprises a first work function voltage, and after annealing, the annealed thick metal/metal nitride layer comprises a second, different work function voltage.

10. The semiconductor device of claim 8, wherein the first, second, and third thin metal/metal nitride layers comprise of amorphous or polycrystalline form as deposited, and a changed microstructure when annealed.

11. The semiconductor device of claim 8, wherein the first thick metal/metal nitride layer comprise a poly crystalline structure as deposited.

12. The semiconductor of claim 8, wherein the thickness of each of the first, second, and third thin metal/metal nitride layers is 10-100 Angstroms.

13. A computer program product, resident on a computer readable medium operable to control a system to fabricate a first gate electrode having a first working function and a second gate electrode having a second working function, the computer program product comprising:

instruction code to form a first well of a first conductivity type and a second well of a second conductivity type;

instruction code to deposit a gate dielectric layer over at least a portion of the first and second wells;

instruction code to form a multi-layer stack over the dielectric layer which extends over the first well, the multi-layer stack comprising two or more thin metal/metal nitride layers;

instruction code to deposit a thick metal/metal nitride layer over (i) the multi-layer stack to form the first gate electrode, and (ii) the gate dielectric layer portion which extends over the second well to form the second gate electrode; and

instruction code to anneal the first and second gate electrodes.

14. The computer program product of claim 13, further comprising instruction code to remove the multi-layer stack from the area of the second well.

15. The computer program product of claim 13, wherein the instruction code to anneal the first and second gate electrodes comprises instruction code to thermally anneal the first and second gate electrodes.

16. The computer program product of claim 13, wherein the thin metal/metal nitride layers comprises a metal or metal nitride from the group consisting of Ti, Ta, Hf, Nb, Mo, Zr, and W and their nitrides.

17. The computer program product of claim 13, wherein the thick metal/metal nitride comprises a metal/metal nitride from the group consisting of Ti, Ta, Hf, Nb, Mo, Zr and W and their nitrides.

18. The computer program product of claim 13, wherein the multi-stack comprises three thin metal/metal nitride layers.

19. The computer program product of claim 13, wherein the gate dielectric layer comprises material from the group consisting of silicon dioxide, silicon nitride, oxynitride, silicate, hafnium oxide, aluminum oxide, BST, and tantalum pentoxide.

20. A semiconductor device having a first well of a first conductivity type and a second well of a second conductivity type, the semiconductor device comprising:

gate dielectric layer means extending over at least a portion of the first well and the second well;

first gate electrode means disposed on the gate dielectric layer means and extending over the first well, the first gate electrode means comprising a multi-layer stack, comprising;

(i) a first thin metal/metal nitride layer disposed on the gate dielectric layer;

(ii) a second thin metal/metal nitride layer disposed on the first thin metal/metal nitride layer;

(iii) a third thin metal/metal nitride layer disposed on the second thin metal/metal nitride layer; and

(iv) a first thick metal/metal nitride layer disposed on the third thin metal/metal nitride layer

first source electrode means and first drain electrode means formed in the first well adjacent to the first gate electrode means;

second gate electrode means disposed on the gate dielectric layer and extending over the second well, the second gate electrode means comprising a portion of the first thick metal/metal nitride layer; and

second source electrode means and second drain electrode means formed in the second well adjacent to the second gate electrode means.