Package having bond-sealed underbump

• US 20050275072A1
• Filed: 05/26/2004
• Published: 12/15/2005
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Haluzak, Charles C., Truninger, Martha A., Michael, Donald L.
• Granted Patent: US 7,067,355 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate

Abstract

A package for containing microelectromechanical devices includes a first substrate wafer, and a second substrate wafer made of an optical quality material. An underbump is interposed between the first and second substrate wafers. The underbump is composed of a standoff region and a localized bond region. The first and second substrate wafers and the underbump define a chamber that contains at least one microelectronic device.

Claims

1. A microelectromechanical device package, comprising:

a first substrate wafer;

a second substrate wafer, the second substrate wafer composed of an optical quality material; and

an underbump interposed between the first substrate wafer and the second substrate wafer, the underbump composed of a standoff region and a localized bond region, wherein the first and second substrate wafers and underbump define a chamber; and

at least one microelectronic device operatively disposed within the chamber.

2. The microelectromechanical device package of claim 1 wherein the underbump further comprises at least one fill port extending from an outer surface of the package to the chamber, the fill port having a metallized surface and adapted to be sealed.

3. The microelectromechanical device package of claim 1 wherein the underbump has a height ranging between about 3 μ

m and about 20 μ

m.

4. The microelectromechanical device package of claim 1 wherein the underbump is integral to at least one of the first substrate wafer and the second substrate wafer and is in sealed contact with the other substrate wafer.

5. The microelectromechanical device package of claim 1 wherein the standoff region includes at least one of silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

6. The microelectromechanical device package of claim 1 wherein the localized bond region includes at least one of nickel, gold, tin, alloys thereof, and mixtures thereof.

7. The microelectromechanical device package of claim 1 wherein the underbump is formed on one of the first and second substrate wafers, and the standoff region of the underbump has a face distal to the substrate wafer on which it is formed.

8. The microelectromechanical device package of claim 7 wherein the localized bond region is positioned on the distal face of the standoff region and is bonded to the other of the first and second substrate wafers.

9. The microelectromechanical device package of claim 1, further comprising a depression defined in at least one of the first and second substrate wafers.

10. The microelectromechanical device package of claim 9 wherein the depression is defined in the first substrate wafer and the underbump is defined on the first substrate wafer.

11. The microelectromechanical device package of claim 1 wherein the second substrate wafer is composed of optical quality glass.

12. The microelectromechanical device package of claim 1 wherein the chamber contains one of a functional fluid and gas sealed therein.

13. A microstructure for packaging a microelectronic device, comprising;

a first substrate wafer;

a second substrate wafer a spaced distance from the first substrate wafer; and

a structure interposed between the first substrate wafer and the second substrate wafer, the structure defining a chamber containing a functional fluid, the structure comprising a standoff region positioned on the second substrate wafer and a metallized layer positioned on the standoff region.

14. The microstructure of claim 13 wherein the standoff region further comprises at least one fill port defined therein, the fill port extending from an exterior surface of the standoff region to the chamber, the fill port having a metallized inner surface adapted to receive a plug in sealing attachment thereto.

15. The microstructure of claim 14, further comprising an adhesion promoting layer disposed on the first substrate wafer, the layer adapted to enhance adhesion between the metallized layer and the first substrate wafer.

16. The microstructure of claim 13, further comprising a depression defined in the second substrate wafer, the depression bounded by the standoff region.

17. The microstructure of claim 13 wherein the microelectronic device is contained in the chamber and wherein the microelectronic device is at least one of micro-opto-electro-mechanical systems, micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors and micro-actuators.

18. The microstructure of claim 13 wherein the standoff region is composed of silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

19. The microstructure of claim 13 wherein the metallized layer contains a metal solder.

20. The microstructure of claim 13 wherein the structure has a height ranging between about 3 μ

m and about 20 μ

m.

21. The microstructure of claim 13 wherein the second substrate wafer is composed of optical quality glass.

22. The microstructure of claim 13 wherein the first substrate wafer is composed of silicon.

23. A method for fabricating an electronic device package structure comprising the steps of:

establishing an underbump on a first substrate wafer, the underbump composed of a localized bond region deposited in overlying relationship to a standoff material; and

adhering the first substrate wafer having the underbump positioned thereon to a second substrate wafer, thereby defining a chamber adapted to contain the electronic device therein.

24. The method of claim 23 wherein establishing the underbump comprises:

establishing the standoff material on the first substrate wafer;

depositing at least one bond material layer over the standoff material, thereby forming a stack; and

configuring the stack into an underbump.

25. The method of claim 24, further comprising the step of establishing an adhesion layer over the standoff material prior to establishing the at least one bond material layer.

26. The method of claim 25 wherein the adhesion layer includes at least one of tantalum and a tantalum-containing compound, and the at least one bond material layer includes at least one layer containing tin and at least one layer containing gold.

27. The method of claim 26, further comprising:

masking the stack with at least one resist material;

sequentially etching the adhesion layer and the at least one bond material layer into an underbump pattern;

masking the standoff material after the at least one bond material layers have been etched; and

etching the standoff material into the underbump pattern.

28. The method of claim 24 wherein configuring the stack comprises:

masking the stack with at least one resist material;

etching the at least one bond material layer into an underbump pattern;

masking the standoff material after the at least one bond material layer has been etched; and

etching the standoff material into the underbump pattern.

29. The method of claim 23 wherein adhering comprises one of anodically bonding and soldering the localized bond region of the underbump to the second substrate wafer.

30. The method of claim 23 wherein the material includes at least one of tetra-orthosilicate glass, silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

31. The method of claim 23, further comprising preparing at least one breach cut in the underbump, the breach cut extending from an exterior surface of the underbump to the chamber defined thereby, the breach cut preparing step occurring prior to the adhering step.

32. The method of claim 31 wherein the localized bond region is a metal material, and the method further comprises depositing the metal material on the underbump and the breach cut prior to adhering the underbump to the second substrate wafer.

33. The method of claim 32, further comprising hermetically sealing the breach cut by soldering after adhering the underbump to the second substrate wafer.

34. The method of claim 23, further comprising depositing a protective layer on the first substrate wafer, the protective layer positioned on a face of the first substrate wafer opposed to the underbump, the protective layer deposited prior to establishing the underbump.

35. The method of claim 34 wherein the first substrate wafer is optical quality glass and the standoff material is composed of at least one of tetraethyl orthosilicate glass and polysilicon glass.

36. The method of claim 34, further comprising the steps of:

removing the protective layer subsequent to establishing the underbump; and

depositing an anti-reflective coating on the face of the first substrate wafer after removing the protective layer.

37. An integrated circuit, comprising:

a semiconductor substrate;

an optical quality glass substrate positioned a spaced distance from the semiconductor substrate;

an underbump interposed between the semiconductor substrate and the optical quality glass substrate, the underbump composed of a standoff region and a localized high-temperature bond region, wherein the semiconductor substrate, the optical quality glass substrate and the underbump define a chamber; and

at least one microelectromechanical device operatively disposed within the chamber.

38. The integrated circuit of claim 37 wherein the underbump has a height ranging between about 3 μ

m and about 20 μ

m.

39. The integrated circuit of claim 37 wherein a material employed in the standoff region includes at least one of tetra-orthosilicate glass, silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

40. The integrated circuit of claim 37 wherein the standoff region comprises a material having a higher melting temperature than a material employed in the localized high-temperature bond region.

41. The integrated circuit of claim 40 wherein the material employed in the localized high-temperature bond region is solder materials.

42. The integrated circuit of claim 41 wherein the solder materials are at least one of nickel, gold, tin, alloys thereof, and mixtures thereof.

43. The integrated circuit of claim 37 wherein the underbump is formed on the optical quality glass substrate, the standoff region has a face distal to the optical quality glass substrate, and wherein the localized high-temperature bond region is positioned on the distal face of the standoff region and is bonded to the semiconductor substrate.

44. The integrated circuit of claim 37, further comprising a depression defined in at least one of the semiconductor substrate and the optical quality glass substrate, the depression being bounded by the underbump.

45. The integrated circuit of claim 37 wherein the underbump further comprises at least one fill port extending from an exterior surface of the underbump to the chamber, the fill port having a metallized surface and adapted to be hermetically sealed by soldering.

46. The integrated circuit of claim 37 wherein the chamber contains a functional fluid sealed therein, and wherein the microelectromechanical device is at least one of micro-opto-electro-mechanical devices, micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors and micro-actuators.

47. A display device, comprising:

a light source for providing a beam of light along a light path;

a light modulating device on the light path for selectively reflecting a portion of the beam of light along a second light path in response to image data signals;

a controller for providing image data signals to a micromirror device; and

at least one element on the second light path for resolving the selectively reflected light into an image;

wherein the light modulating device comprises;

a first substrate wafer;

a second substrate wafer;

an underbump interposed between the first substrate wafer and the second substrate wafer, the underbump composed of a standoff region and a localized bond region, wherein the first and second substrate wafers and underbump define a chamber; and

at least one microelectromechanical device operatively disposed within the chamber.

48. The display device of claim 47 wherein the underbump has a height ranging between about 3 μ

m and about 20 μ

m.

49. The display device of claim 47 wherein the standoff region includes at least one of tetra-orthosilicate glass, silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

50. The display device of claim 47 wherein the localized bond region comprises at least one of nickel, gold, tin, alloys thereof, and mixtures thereof.

51. The display device of claim 47 wherein at least one of the first and second substrate wafers is composed of optical quality glass.

52. The display device of claim 47 wherein the chamber contains a functional fluid sealed therein.

53. A spatial light modulator, comprising:

a first substrate wafer, the first substrate layer composed of optical quality glass and having a face;

a second substrate wafer a spaced distance from the first substrate wafer;

an underbump interposed between the first substrate wafer and the second substrate wafer, the underbump composed of a standoff region and a localized bond region, wherein the first substrate wafer, second substrate wafer and underbump define a chamber; and

at least one microelectromechanical device operatively disposed within the chamber.

54. The spatial light modulator of claim 53 wherein the standoff region includes at least one of tetra-orthosilicate glass, silica glass, phosphosilicate, polysilicon, borosilicate glass, titanium silicate glass, polysilazane, tetraethyl-ortho-silicate glass, metal-organic spin-on coatings, nickel, copper, and mixtures thereof.

55. The spatial light modulator of claim 53 wherein the localized bond region is at least one of nickel, gold, tin, alloys thereof, and mixtures thereof.

56. The spatial light modulator of claim 53 wherein the underbump is contiguously connected to the face of the first substrate wafer and is in sealed contact with the second substrate wafer.

57. The spatial light modulator of claim 53 wherein the underbump is formed on the face of the first substrate wafer, wherein the standoff region has a face distal to the first substrate wafer, and wherein the localized bond region is positioned on the distal face of the standoff region and is in sealed contact with the second substrate wafer.

58. The spatial light modulator of claim 53 wherein the first substrate wafer includes a depression defined therein, and wherein the depression is bounded by the underbump.

59. The spatial light modulator of claim 53 wherein the chamber contains a functional fluid sealed therein.

60. The spatial light modulator of claim 53 wherein the underbump further comprises at least one fill port extending from an exterior surface of the underbump to the chamber, the fill port having a metallized surface.

61. A microelectromechanical device package, comprising:

a first substrate;

a second substrate;

means for connecting the first substrate to the second substrate, the connecting means interposed between the first and second substrates such that the first and second substrates are positioned a spaced distance from one another and define at least one chamber therebetween;

means, defined within the connecting means, for filling the chamber with at least one of a functional fluid and gas after the first and second substrates are connected; and

means for performing at least one microelectromechanical function, the microelectromechanical function performing means operatively disposed in the chamber.