Embedded chip semiconductor having dual electronic connection faces

• US 20050275081A1
• Filed: 06/12/2004
• Published: 12/15/2005
• Est. Priority Date: 06/12/2004
• Status: Abandoned Application

• Current Assignee: Roger Chang
• Original Assignee: Roger Chang
• Inventors: Chang, Roger
• Application Number:
  US10/866,292
• Publication Number:
  US 20050275081A1
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An embedded chip semiconductor has a substrate, at least one chip, an encapsulant, two circuit patterns and multiple contact vias. The substrate has a top surface, a bottom surface and at least one chip recess. The at least one chip has multiple terminals and is mounted in a corresponding chip recess. The thickness of the chip is equal to or less than the thickness of the substrate. The encapsulant is formed in the chip recess to hold the chip. The circuit patterns are respectively formed on the top and bottom surfaces of the substrate and one of the circuit patterns is connected to the multiple terminals of the chip. The two circuit patterns on two surfaces of the substrate are connected through the multiple contact vias. Therefore, the semiconductor has dual electronic connection faces to be suitable for different applications.

Claims

1. An embedded chip semiconductor having dual electronic connection faces, comprising:

a substrate separated from a print circuit board having a top surface, a bottom surface and at least one chip recess;

at least one chip mounted respectively in the at least one chip recess and having outer edges, a top face, a bottom face and multiple terminals formed on the bottom face;

a first circuit pattern and a second circuit pattern respectively formed on the top and bottom surfaces of the substrate, wherein

the first circuit pattern is higher than the top face of the at least one chip; and

the second circuit pattern and has an inner area corresponding to the at least one chip recess and an outer area outside the inner area, wherein the terminals on the at least one chip are connected to the second circuit pattern;

an encapsulant vacuum press laminated in the at least one chip recess around the edges of the at least one chip to insulate the chip from the substrate, and flush with the top surface of the substrate; and

multiple contact vias respectively formed through the substrate to connect to the first and the second circuit patterns.

2. The semiconductor as claimed in claim 1, wherein the top face of each one of the at least one chip faces to the first circuit pattern and the terminals of each one of the at least one chip are connected to the second circuit pattern through multiple solder bumps.

3. The semiconductor as claimed in claim 1, wherein the top face of each one of the at least one chip is mounted on the second circuit pattern and the terminals on the bottom face of each one of the at least one chip are connected to the second circuit pattern through multiple wire bondings.

4. The semiconductor as claimed in claim 2, wherein the substrate is metallic and the semiconductor further comprises:

a first insulation layer vacuum press laminated among the first circuit pattern, the top surface of the substrate and the encapsulant;

a second insulation layer formed between the second circuit pattern and the bottom surface of the substrate; and

multiple separations respectively vacuum press laminated between a portion of each contact via and the substrate, wherein each contact via is further formed through the first and second insulation layers to connect to the first and second circuit patterns.

5. The semiconductor as claimed in claim 3, wherein the substrate is metallic and the semiconductor further comprises:

a first insulation layer vacuum press laminated among the first circuit pattern, the top surface of the substrate and the encapsulant;

a second insulation layer formed between the second circuit pattern and the bottom surface of the substrate; and

multiple separations respectively vacuum press laminated between a portion of each contact via and the substrate, wherein each contact via is further formed through the first and second insulation layers to connect to the first and second circuit patterns.

6. The semiconductor as claimed in claim 4, further comprising two protective layers respectively formed on portions of the first and second circuit patterns.

7. The semiconductor as claimed in claim 5, further comprising two protective layers respectively formed on portions of the first and second circuit patterns.

8. The semiconductor as claimed in claim 6, wherein the outer area of the second circuit pattern is extended outward to form multiple bumps.

9. The semiconductor as claimed in claim 7, wherein the outer area of the second circuit pattern is extended outward to form multiple bumps.

10. The semiconductor as claimed in claim 2, wherein the substrate is nonmetallic.

11. The semiconductor as claimed in claim 3, wherein the substrate is nonmetallic.

12. The semiconductor as claimed in claim 1, wherein the second circuit pattern comprises multiple bottom bumps, that are formed by etching a bottom of the second circuit pattern.

13. The semiconductor as claimed in claim 12, wherein the bottom bumps are pillars.