Capping of metal interconnects in integrated circuit electronic devices
First Claim
Patent Images
1. A method for forming a multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising:
- depositing a first metal cap layer over the metal-filled interconnect feature in a first deposition process which constitutes electroless metal deposition from an electroless bath comprising a source of metal ions and a reducing agent; and
depositing a second metal cap layer over the first metal cap layer in a second deposition process distinct from the first deposition process to thereby form the multilayer metal cap as a permanent component distinct from the metal-filled interconnect feature.
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Abstract
A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.
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Citations
67 Claims
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1. A method for forming a multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising:
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depositing a first metal cap layer over the metal-filled interconnect feature in a first deposition process which constitutes electroless metal deposition from an electroless bath comprising a source of metal ions and a reducing agent; and
depositing a second metal cap layer over the first metal cap layer in a second deposition process distinct from the first deposition process to thereby form the multilayer metal cap as a permanent component distinct from the metal-filled interconnect feature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 51)
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28. A method for forming a multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising:
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depositing a first metal cap layer over the metal-filled interconnect feature in a first deposition process which constitutes noble metal immersion deposition from a solution comprising a source of noble metal ions;
depositing a second metal cap layer over the first metal cap layer in a second deposition process distinct from the first deposition process; and
depositing a third metal cap layer over the second metal cap layer in a third deposition process distinct from the second deposition process. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52)
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53. A method for forming a multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising:
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depositing a catalytic first metal cap layer over the metal-filled interconnect feature in a first deposition process; and
depositing a second metal cap layer over the first metal cap layer in a second deposition process distinct from the first deposition process, wherein the second deposition process comprises autocatalytic deposition and deposition catalyzed by the first metal cap layer. - View Dependent Claims (54, 55)
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56. A multilayer cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising:
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a first metal cap layer over the metal-filled interconnect feature; and
a second metal cap layer over the first metal cap layer, wherein the first and second metal cap layers are components of the multilayer metal cap which constitutes a permanent component distinct from the metal interconnect feature. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67)
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Specification