Asymmetrical SRAM device and method of manufacturing the same

• US 20050275117A1
• Filed: 03/28/2005
• Published: 12/15/2005
• Est. Priority Date: 06/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Jong-hyon, Kang, Tae-woong
• Granted Patent: US 7,486,543 B2
• Time in Patent Office: Days
• US Class Current: 257/427
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Claims

1. An asymmetrical SRAM device, comprising:

a semiconductor substrate on which a plurality of unit cell regions are defined; and

a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate,

wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

2. The asymmetrical SRAM device as claimed in claim 1, wherein the plurality of active regions comprises:

a first NMOS active region extending in a bar shape;

a second NMOS active region parallel to the first NMOS active region and separated a predetermined distance from the first NMOS active region;

a first PMOS active region having a bar shape and located between the first NMOS active region and the second NMOS active region; and

a second PMOS active region having a bar shape and located between the first PMOS active region and the second NMOS active region.

3. The asymmetrical SRAM device as claimed in claim 2, wherein the second PMOS active region is shifted by a predetermined distance from the first PMOS active region in a lengthwise direction of the active regions.

4. The asymmetrical SRAM device as claimed in claim 2, further comprising:

a first gate electrode extended to contact a predetermined portion of the first NMOS active region and a predetermined portion of the first PMOS active region;

a second gate electrode extended to contact a predetermined portion of the second NMOS active region and a predetermined portion of the second PMOS active region;

a first word line parallel to the first gate electrode and contacting a predetermined portion of the first NMOS active region; and

a second word line parallel to the second gate electrode and contacting a predetermined portion of the second NMOS active region.

5. The asymmetrical SRAM device as claimed in claim 4, further comprising first threshold voltage control ions implanted into the active region, and second threshold voltage control ions for a high voltage transistor implanted into an overlap region of the first gate electrode and the first PMOS active region, an overlap region of the second gate electrode and the second NMOS active region, and an overlap region of the first word line and the first NMOS active region.

6. The asymmetrical SRAM device as claimed in claim 4, further comprising source/drain regions of the MOS transistors respectively formed on the active region on both sides of the first and second gate electrodes and the first and second word lines, a first NMOS transistor and a first pass transistor defined within the first NMOS active region, a second NMOS transistor and a second pass transistor defined within the second NMOS active region, a first PMOS transistor defined within the first PMOS active region, and a second PMOS transistor defined within the second PMOS active region.

7. The asymmetrical SRAM device as claimed in claim 6, further comprising:

a first metal wiring that electrically connects the first gate electrode and the drain of the second NMOS transistor; and

a second metal wiring that electrically connects the second gate electrode and the drain of the first NMOS transistor.

8. An asymmetrical SRAM device, comprising:

a semiconductor substrate on which a plurality of unit cell regions are defined in a matrix;

a plurality of active regions located in each of the unit cell regions and including a first NMOS active region on which a first NMOS transistor and a first pass transistor will be formed, a second NMOS active region on which a second NMOS transistor and a second pass transistor will be formed, a first PMOS active region on which a first PMOS transistor will be formed, and a second PMOS active region on which a second PMOS transistor will be formed;

a gate structure including

a first gate electrode contacting the first NMOS active region and the first PMOS active region,

a second gate electrode contacting the second NMOS active region and the second PMOS active region,

a first word line contacting the first NMOS active region, and

a second word line contacting the second NMOS active region;

a plurality of source and drain regions respectively formed on the active region on both sides of the gate structure to define the first and second NMOS transistors, the first and second PMOS transistors, and the first and second pass transistors; and

a plurality of high voltage control layers formed in the second NMOS transistor region, the first pass transistor region, and the first PMOS transistor region,

wherein each unit cell region is a mirror image of an adjacent one of the unit cell regions with respect to a boundary line between the adjacent unit cell regions, and the plurality of high voltage threshold voltage control layers face another high voltage threshold voltage control layer of the adjacent unit cell region with respect to the boundary line of the unit cell regions.

9. The asymmetrical SRAM device as claimed in claim 8, wherein the first and second NMOS active regions and the first and second PMOS active regions have a bar shape and extend in a same direction.

10. The asymmetrical SRAM device as claimed in claim 9, wherein the first and second PMOS active regions are separated by a predetermined distance and extend parallel to each other, and the first and second PMOS active regions are interposed between the first and second NMOS active regions.

11. The asymmetrical SRAM device as claimed in claim 9, wherein the first and second NMOS active regions are disposed on a substantially same line.

12. The asymmetrical SRAM device as claimed in claim 9, wherein an end of the second PMOS active region is shifted from a corresponding end of the first PMOS active region by a predetermined distance, thereby overlapping a predetermined portion of the second PMOS active region and an isolation film.

13. The asymmetrical SRAM device as claimed in claim 8, wherein the first and second gate electrodes extend parallel to each other, and the first word line extends parallel to the first gate electrode a predetermined distance apart therefrom, and the second word line extends parallel to the second gate electrode a predetermined distance apart therefrom.

14. The asymmetrical SRAM device as claimed in claim 13, wherein the first gate electrode further extends to overlap a predetermined portion of the second PMOS active region, and the first gate electrode overlaps an end of the second PMOS active region.

15. The asymmetrical SRAM device as claimed in claim 13, wherein the second gate electrode further extends to overlap a predetermined portion of the first PMOS active region, and the second gate electrode overlaps an end of the second PMOS active region.

16. The asymmetrical SRAM device as claimed in claim 8, further comprising:

a first metal wiring that electrically connects the first gate electrode and the drain of the second NMOS transistor; and

a second metal wiring that electrically connects the second gate electrode and the drain of the first NMOS transistor.

17. The asymmetrical SRAM device as claimed in claim 8, further comprising threshold voltage control ions at a different concentration from the high voltage threshold voltage control layer implanted in the active region.

18. An asymmetrical SRAM device, comprising:

a plurality of unit cell regions; and

a unit SRAM cell formed on the each unit cell, the unit SRAM cell including

a first inverter having a first PMOS high voltage transistor and a first NMOS transistor,

a second inverter having a second PMOS transistor and a second NMOS high voltage transistor,

a first pass high voltage transistor connected to the second inverter, and

a second pass transistor connected to the first inverter,

wherein the unit SRAM cell is a mirror image of an adjacent unit SRAM cell with respect to a boundary line between adjacent unit SRAM cells, and

the first PMOS high voltage transistor, the second NMOS high voltage transistor, and the first pass high voltage transistor are located adjacent to the boundary line of the unit SRAM cell to face high voltage transistors of adjacent unit SRAM cells.

19. The asymmetrical SRAM device as claimed in claim 18, wherein the unit SRAM cell comprises:

an active region, on which each of the transistors are formed;

a gate electrode structure contacting the active region; and

a source and drain region, each formed on the active region on either side of the gate electrode structure.

20. The asymmetrical SRAM device as claimed in claim 19, wherein the active region comprises:

a first NMOS active region, on which the first NMOS transistor and the first high voltage pass transistor are formed;

a second NMOS active region, on which the second NMOS high voltage transistor and the second pass transistor are formed;

a first PMOS active region, on which the first PMOS high voltage transistor is formed; and

a second PMOS active region, on which the second PMOS transistor is formed,

wherein each of the first and second NMOS active regions and the first and second PMOS active regions are formed in a bar shape extending in a same direction,

the first and second PMOS active regions are parallel to each other spaced apart by a predetermined distance, and

the first and second NMOS active regions are located between the first and second PMOS active regions.

21. The asymmetrical SRAM device as claimed in claim 20, further comprising:

a first gate electrode extended to contact a predetermined portion of the first NMOS active region and a predetermined portion of the first PMOS active region;

a second gate electrode extended to contact a predetermined portion of the second NMOS active region and a predetermined portion of the second PMOS active region;

a first word line parallel to the first gate electrode and contacting a predetermined portion of the first NMOS active region; and

a second word line parallel to the second gate electrode and contacting a predetermined portion of the second NMOS active region.

22. The asymmetrical SRAM device as claimed in claim 19, further comprising:

a first metal wiring that electrically connects an input of the first inverter and an output of the second inverter; and

a second metal wiring that electrically connects an output of the first inverter and an input of the second inverter.

23. A method of manufacturing an asymmetrical SRAM device, comprising:

preparing a semiconductor substrate on which a plurality of unit cell regions are defined;

defining active regions including first and second NMOS active regions and first and second PMOS active regions by forming an isolation film in each unit cell region;

implanting threshold voltage control ions into the entire active regions;

implanting threshold voltage control ions for high voltage transistors into a predetermined portion of the first NMOS active region, a predetermined portion of the second NMOS active region, and a predetermined portion of the first PMOS active region;

forming gate electrodes to contact the active regions; and

forming source and drain regions by implanting a dopant on both sides of the gate electrodes,

wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the unit cell regions with respect to a boundary line between the adjacent unit cell regions, and

the threshold voltage control ions for the high voltage transistors are simultaneously implanted into regions for implanting the threshold voltage control ions for the high voltage transistors of adjacent unit cell regions when implanting ions into the region of the unit cell region, by locating the regions into which the threshold voltage control ions for the high voltage transistors are implanted adjacent to the boundary line of the unit cell region.

24. The method as claimed in claim 23, wherein implanting the threshold voltage control ions comprises:

selectively implanting first threshold voltage control ions into the first and second NMOS active regions; and

selectively implanting second threshold voltage control ions into the first and second PMOS active regions.

25. The method as claimed in claim 23, wherein implanting the threshold voltage control ions for high voltage transistors comprises:

forming a first mask pattern to expose a predetermined portion of the first and second NMOS active regions;

implanting threshold voltage control ions for first high voltage transistors into the exposed first and second NMOS active regions;

removing the first mask pattern;

forming a second mask pattern to expose a predetermined portion of the first and second PMOS active regions;

implanting threshold voltage control ions for second high voltage transistors into the exposed first and second PMOS active regions; and

removing the second mask pattern.

26. The method as claimed in claim 25, wherein the first mask pattern simultaneously exposes the first and second NMOS active regions of the four adjacent unit cell regions.

27. The method as claimed in claim 25, wherein the second mask pattern simultaneously exposes the first PMOS active regions of two adjacent unit cell regions.