High density interconnect system having rapid fabrication cycle

• US 20050275418A1
• Filed: 05/18/2005
• Published: 12/15/2005
• Est. Priority Date: 05/23/2000
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Mok, Sammy, Chong, Fu Chiung, Swiatowiec, Frank John, Parekh, Nitin, Litza, Anna, Shan, Zhaohui, Kao, Andrew, Modlin, Douglas, McKay, Douglas
• Granted Patent: US 7,382,142 B2
• Time in Patent Office: Days
• US Class Current: 324/750.250
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49222 forming array of contacts or terminals

Abstract

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

Claims

1. A probe card interface assembly for establishing connections to one or more bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising:

a motherboard having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

a reference plane defined by at least three points located between the lower planar mounting surface of the motherboard and the semiconductor wafer;

a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe chip assembly mounting surface opposite the upper mounting surface; and

a mechanism for adjusting the planarity of the reference plane with respect to the semiconductor wafer.

2. The probe card interface assembly of claim 1, further comprising:

at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface attached to the probe chip assembly mounting surface of the probe chip assembly mounting system, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein planarity of any of the probing surface and the mounting surface of the probe chip is adjustable through the planarity mechanism.

3. The probe card interface assembly of claim 2, wherein the probe tips are planarized by confining the probe tips in a fixture that is parallel to any of the probing surface and the mounting surface of the probe chip substrate, and applying heat to the probe chip assembly, such that the probe tips conform to the fixture.

4. The probe card interface assembly of claim 2, wherein the planarity adjustment mechanism comprises any of adjustable screws, differential screws, shims, spacers, washers, spring washers, solder bonds, adhesive bonds, springs, and any combination thereof.

5. The probe card interface assembly of claim 2, wherein mounting of the probe chip assembly inherently provides parallelism between any of the probing surface and the mounting surface of the probe chip, and the probe assembly mounting surface of the probe chip assembly.

6. The probe card interface assembly of claim 2, wherein the probe chip assembly is demountable.

7. The probe card interface assembly of claim 2, further comprising:

means for any of measuring and adjusting parallelism between the lower planar mounting surface and any of the probing surface and the mounting surface of the probe chip.

8. The probe card interface assembly of claim 1, further comprising:

an alternate probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein the mounting surface of the alternate probe chip assembly is mountable to the lower planar surface of the probe card interface assembly.

9. The probe card interface assembly of claim 8, wherein the alternate probe chip assembly is mountable in place of the first probe chip assembly to provide planarity without further calibration.

10. The probe card interface assembly of claim 1, further comprising:

means for any of measuring and adjusting parallelism between the lower planar mounting surface and any of the reference plane and the probe chip assembly mounting surface.

11. The probe card interface assembly of claim 1, wherein the probe chip assembly mounting system comprises:

a lower Z-block comprising a substrate having an interposer contacting surface and a probe chip mounting surface opposite the interposer contacting surface, a first plurality of electrical contact pads arranged on the interposer contacting surface, a corresponding second plurality of bonding pads on the probe chip mounting surface, and electrical connections extending from each of the contact pads in the first plurality of bonding pads to each of the corresponding bonding pads in the second plurality of bonding pads; and

an upper interface located between the lower Z-block and the motherboard, comprising a plurality of electrical contacts;

wherein the lower Z-block is attached to the motherboard with the interposer contacting surface oriented to be parallel with the wafer prober mounting surface.

12. The probe card interface assembly of claim 11, wherein the substrate of the lower Z-block comprises any of a ceramic, a multilayered ceramic, and a co-fired ceramic.

13. The probe card interface assembly of claim 11, further comprising:

at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface soldered to the probe chip mounting surface of the lower Z-block, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts;

wherein the planarity mechanism is controllable to adjust the reference plane to affect planarity between the probing surface and the semiconductor wafer.

wherein planarity of any of the probing surface and the mounting surface of the probe are adjustable through the planarity mechanism.

14. The probe card interface assembly of claim 13, wherein the upper interface comprises any of:

at least one interposer located between the lower Z-block and the mother board, each of the at least one interposer comprising an upper surface and a lower surface opposite the upper surface, a plurality of compliant electrical contacts on the upper surface, a plurality of electrical contacts on the lower surface, and a plurality of electrically conductive connections between the plurality of compliant electrical contacts and the plurality of electrical contacts; and

a motherboard Z-Block having a first surface and a second surface opposite the first surface, and a plurality of solder bonds between the second surface and the motherboard.

15. The probe card interface assembly of claim 14, wherein the motherboard Z-block contains fan-out electrical connections extending there through.

16. The probe card interface assembly of claim 14, wherein the compliant electrical contacts are plated.

17. The probe card interface assembly of claim 14, wherein the plurality of electrical contacts on the lower surface of the interposer comprise any of solder balls and spring probes.

18. The probe card interface assembly of claim 17, wherein the spring probes are plated.

19. The probe card interface assembly of claim 14, further comprising:

means for adjusting parallelism between the probing surface of the probe chip and any of the interposer contacting surface of the lower Z-block and the upper surface of the interposer.

20. The probe card interface assembly of claim 14, further comprising:

means for any of adjusting parallelism between the lower planar mounting surface and the first surface of the motherboard z-block.

21. The probe card interface assembly of claim 11, wherein the electrical contact pads arranged on the interposer contacting surface of the lower Z-block are spaced at a larger pitch than the spacing of the corresponding second plurality of bonding pads on the probe chip mounting surface of the lower Z-block.

22. The probe card interface assembly of claim 2, wherein the spring probes comprise any of stress metal springs, flexible springs, compliant springs, and elongate resilient probe elements.

23. A process for establishing connections to bonding pads on at least one integrated circuit device located on a semiconductor wafer, comprising the steps of:

providing a motherboard comprising a substrate having an upper surface, a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, and a plurality of electrical connections extending between the lower planar mounting surface opposite the upper surface;

defining a reference plane by at least three points located between the lower surface of the motherboard and the semiconductor wafer;

providing a probe chip assembly mounting system comprising at least one component having an upper mounting surface and a probe assembly mounting surface opposite the upper mounting surface; and

adjusting the planarity of the reference plane with respect to the semiconductor wafer.

24. The process of claim 23, further comprising the steps of:

providing a probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface attached to the probe chip assembly mounting surface of the probe chip assembly mounting system, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts; and

adjusting the reference plane to affect planarity between any of the probing surface, the mounting surface, and the probe tips of the probe chip and the semiconductor wafer.

25. The process of claim 24, further comprising the steps of:

mounting the mother board to a prober; and

testing at least one integrated device located on a semiconductor wafer;

wherein the probe tips are sufficiently planar to the semiconductor wafer without further adjustment of planarity.

26. The process of claim 24, further comprising the steps of:

confining the probe tips in a fixture that is parallel to any of the probing surface and the bonding surface of the probe chip substrate, and

applying heat to the probe chip assembly, such that the probe tips conform to the fixture.

27. The process of claim 26, further comprising the step of:

plating the probe tips at any of before and after the heating step.

28. The process of claim 24, further comprising the steps of:

removing the probe chip from the probe assembly mounting surface; and

mounting any of the same probe chip and an alternate probe chip to the probe assembly mounting surface to provide planarity without further calibration.

29. The process of claim 23, further comprising any of:

measuring and adjusting parallelism between the reference plane and the lower planar mounting surface.

30. The process of claim 23, further comprising the steps of:

providing a lower Z-block comprising a substrate having an interposer contacting surface and a probe chip mounting surface opposite the interposer contacting surface, a first plurality of electrical contact pads arranged on the interposer contacting surface, a corresponding second plurality of bonding pads on the probe chip mounting surface, and electrical connections extending from each of the contact pads in the first plurality of bonding pads to each of the corresponding bonding pads in the second plurality of bonding pads;

providing an upper interface located between the lower Z-block and the mother board, comprising a plurality of electrical contacts; and

attaching the lower Z-block to the mother board with the interposer contacting surface oriented to be parallel with the lower planar mounting surface.

31. The process of claim 30, further comprising the steps of:

providing at least one probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, the mounting surface soldered to the probe chip mounting surface of the lower Z-block, a plurality of spring probes on the probing surface extending from the probing surface to define a plurality of probe tips arranged to correspond to the bonding pads, a corresponding second plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding second plurality of electrical contacts; and

adjusting the reference plane to affect planarity between the probing surface and the semiconductor wafer.

32. The process of claim 30, wherein the upper interface comprises any of:

at least one interposer located between the lower Z-block and the mother board, each of the at least one interposer comprising an upper surface and a lower surface opposite the upper surface, a plurality of compliant electrical contacts on the upper surface, a plurality of electrical contacts on the lower surface, and a plurality of electrically conductive connections between the plurality of compliant electrical contacts and the plurality of electrical contacts; and

a motherboard Z-Block having a first surface and a second surface opposite the first surface, and a plurality of solder bonds between the second surface and the motherboard.

33. A method of production of a rapid cycle time customizable probe card for testing semiconductor wafers comprising:

providing customizable components with rapid design and fabrication process cycle times,

providing standard components where the design and fabrication process cycle time of at least one of the standard components is longer than the rapid cycle time for the customizable components; and

assembling and testing probe card from the customizable components and the standard components, wherein the time to assemble and test the probe card is equal to that of the longest of the customizable components.

34. The method of claim 33,

wherein the customizable components having rapid cycle times comprise any of a mother board and a probe chip assembly;

and

wherein the standard components having cycle times that may be longer than those of the mother board and probe chip comprise any of a probe tip support substrate and at least one interposer.

35. A method for fabrication an interconnection assembly comprising a stacked plurality of structures, comprising the steps of:

providing a plurality of structures; and

improving the planarity of the interconnection assembly by any of improving the planarity of at least one of the structures before assembly, and compensating for non-planarity in the structures during assembly by varying the spacing of one or more connections between at least two of the structures.

36. The method of claim 35, wherein the interconnection assembly is a probe card assembly for connection to a semiconductor wafer, wherein the structures are any of a probe chip, a Z-Block, a mother board, and an interposer, and wherein the connections comprise any of solder bonds, spring probes, and mechanical connections.

37. The method of claim 35, wherein the planarity improvement comprises any of:

planarizing spring probes extending from a probe chip substrate; and

controllably establishing a plurality of solder bonds between at least two of the plurality of structures by varying the spacing of at least one of the plurality of connections between the at least two structures.

38. A process, comprising the steps of:

providing a probe chip comprising a probe chip substrate having a probing surface and a mounting surface opposite the probing surface, a plurality of spring probes on the probing surface and extending from the probing surface to define a plurality of probe tips, a corresponding plurality of electrical contacts located on the mounting surface, and electrical connections extending from each of the spring probes to each of the corresponding plurality of electrical contacts;

confining the probe tips in a fixture that is parallel to any of the probing surface and the bonding surface of the probe chip substrate, and

applying heat to the probe chip, such that the probe tips conform to the fixture.

39. The process of claim 38, further comprising the step of:

plating the probe tips at any of before and after the heating step.

40. The process of claim 38, wherein the spring probes comprise any of stress metal springs, flexible springs, compliant springs, and elongate resilient probe elements.