Nonvolatile memory apparatus

• US 20050276110A1
• Filed: 06/13/2005
• Published: 12/15/2005
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kasai, Hideo, Sakurai, Ryotaro, Chigasaki, Hideo
• Granted Patent: US 7,170,787 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.

Claims

1. A nonvolatile memory apparatus comprising:

a memory array having a plurality of nonvolatile memory cells;

a stepped-up/down power supply circuit for generating a first voltage for supplying to a nonvolatile memory cell from an external power voltage; and

a stepped-down power supply unit for generating a second voltage for supplying to an internal circuit from the external power voltage,

wherein in an operating mode, said stepped-down power supply unit generates the second voltage by stepped down from the external power voltage and supplies the second voltage to said internal logical circuits, and

wherein in a standby mode, said stepped-down power supply unit determines the level of the external power voltage, and when the external power voltage is lower than a determination voltage level, supplies the external power voltage as the second voltage to said internal logical circuits, and when the external power voltage is higher than the determination voltage level, supplies a level shifted voltage, which is level shifted by the threshold voltage of a first MOS transistor, from the external power voltage as the second voltage to said internal logical circuits.

2. The nonvolatile memory apparatus according to claim 1,

wherein said stepped-down power supply unit comprises:

a voltage determining unit which determines the level of the external power voltage and outputs a control signal on the basis of the result of that determination;

an operating mode power voltage circuit which, on the basis of the control signal from said voltage determining unit, generates a stepped-down power voltage from the external power voltage in the operating mode and supplies it to said internal logical circuits; and

a standby mode stepped-down power supply circuit which, on the basis of the control signal from said voltage determining unit, when in the standby mode the external power voltage is lower than the determination voltage level, supplies said internal logical circuits with that external power voltage as the stepped-down power voltage, and when the external power voltage is higher than the determination voltage level, supplies said internal logical circuits with the stepped-down power voltage resulting from the level-shifting of the external power voltage with the threshold voltage of the stepping-down MOS transistors.

3. The nonvolatile memory apparatus according to claim 2,

wherein said standby mode stepped-down power supply circuit comprises:

first switching means which outputs an external power voltage on the basis of a control signal; and

a level shift unit comprising second switching means which outputs an external power voltage on the basis of a control signal and said stepping-down MOS transistors which are connected to said second switching means and level-shift an external power voltage outputted via said second switching means, and

wherein said voltage determining unit, in the standby mode, so outputs a control signal as to actuate said first switching means when the external power voltage is lower than the determination voltage level, or so outputs a control signal as to actuate said second switching means when the external power voltage is higher than the determination voltage level.

4. The nonvolatile memory apparatus according to claim 3,

wherein said level shift unit, when the external power voltage is higher than said determination voltage level, makes variable the extent of level shift by said stepping-down MOS transistor according to the level of the external power voltage.

5. The nonvolatile memory apparatus according to claim 4,

wherein the extent of level shift by said stepping-down MOS transistors is enabled to vary by making the number of connection stages of said stepping-down MOS transistors variable.

6. The nonvolatile memory apparatus according to claim 5,

wherein said operating mode power voltage circuit comprises:

a mode detecting unit which detects whether the operating mode is said normal operating mode or a low power consumption mode and outputs a control signal on the basis of the result of the detection;

a first operating mode power voltage circuit which, on the basis of the control signal outputted from said mode detecting unit, generates a stepped-down power voltage from the external power voltage and supplies it to said internal logical circuits; and

a second operating mode power voltage circuit whose current drive capacity is set smaller than that of said first operating mode power voltage circuit; and

wherein said mode detecting unit,

actuates, when it detects the normal operating mode, said first operating mode power voltage circuit to output a control signal so as to stop said second operating mode power voltage circuit, and

actuates, when it detects the low power consumption mode, said second operating mode power voltage circuit to output a control signal so as to stop said first operating mode power voltage circuit.

7. The nonvolatile memory apparatus according to claim 6,

wherein said first operating mode power voltage circuit, when in the normal mode said voltage determining unit determines the level of the external power voltage to be lower than the determination voltage level, supplies said internal logical circuits with that external power voltage as the stepped-down power voltage.