Reduced power programming of non-volatile cells

• US 20050276118A1
• Filed: 06/10/2004
• Published: 12/15/2005
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Maayan, Eduardo
• Granted Patent: US 7,366,025 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Claims

1. A method comprising:

programming a non-volatile memory cell without having a direct current flowing from a positive supply to ground through a memory array in which said cell forms a part.

2. The method of claim 1 and wherein said programming comprises:

disconnecting a source of a non-volatile memory cell from a ground voltage; and

after said source is disconnected, providing a programming voltage to a drain of said cell.

3. The method according to claim 2 and wherein said disconnecting comprises disconnecting a ground supply from a global bit line.

4. The method according to claim 2 and wherein said disconnecting comprises disconnecting a local bit line forming said source from a global bit line carrying said ground voltage.

5. The method of claim 1 and wherein said programming comprises:

providing a programming voltage to a drain of said cell; and

after said drain voltage is applied, disconnecting a source of a non-volatile memory cell from a ground voltage.

6. The method according to claim 5 and wherein said disconnecting comprises disconnecting a ground supply from a global bit line.

7. The method according to claim 5 and wherein said disconnecting comprises disconnecting a local bit line forming said source from a global bit line carrying said ground voltage.

8. The method of claim 1 wherein said non-volatile memory cell is an NROM cell.

9. The method of claim 1 wherein said memory array is a segmented virtual ground array.

10. The method of claim 9 wherein said array has isolation slices therein.

12. The method according to claim 10 and wherein said plurality of cells comprises cells in a row.

13. The method according to claim 10 and wherein said plurality of cells comprises cells in a column.

14. The method according to claim 10 and wherein said programming comprises:

charging a word line;

charging said global bit line and then selectively turning ON and OFF select transistors connecting said global bit line to local bit lines associated with said group of cells.

15. The method according to claim 10 and wherein said programming comprises charging said global bit line, turning ON select transistors connecting said global bit line to a local bit line associated with said cells and then selectively charging and discharging word lines associated with said group of cells.

16. The method of claim 10 wherein said non-volatile memory cells are NROM cells.

17. The method of claim 10 wherein said non-volatile memory cells are arranged in a segmented virtual ground array configuration.

18. The method of claim 17 wherein said array has isolation slices therein.

11. A method comprising:

programming a plurality of non-volatile memory cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses.

19. A method comprising:

programming a non-volatile memory cell with transient currents.

20. The method of claim 19 and wherein said programming comprises:

providing a programming voltage to a drain of said cell; and

after said drain voltage is applied, disconnecting a source of a non-volatile memory cell from a ground voltage.

21. The method of claim 19 wherein said non-volatile memory cells are NROM cells.

22. The method of claim 19 wherein said non-volatile memory cells are arranged in a segmented virtual ground array configuration.

23. The method of claim 22 wherein said array has isolation slices therein.