Hybrid wired and wireless chip-to-chip communications

• US 20050276322A1
• Filed: 06/14/2004
• Published: 12/15/2005
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C.
• Granted Patent: US 7,535,958 B2
• Time in Patent Office: Days
• US Class Current: 375/239
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

A hybrid wireless and wired system distributes precise timing and synchronization information among the nodes over a wired interconnect structure while data is transmitted wirelessly using ultra-wideband radio over short distances. The timing information communicated over the wired interconnect structure is used to establish a baseline timing reference for the wireless transmitters, receivers and transceivers on the nodes of the communication network. Using a common timing reference, a mesochronous communication system is established for chip-to-chip wireless data transmission.

Claims

1. A method for wireless communications between a first node and a second node, comprising:

delivering a timing reference signal via a wired interconnect structure to the first node and the second node;

transmitting a radio signal in response to the timing reference signal at the first node, the radio signal carrying data; and

receiving the radio signal in response to the timing reference signal at the second node.

2. The method of claim 1, wherein the radio signal carries data by pulse position modulation.

3. The method of claim 1, wherein the radio signal comprises an ultra-wide band radio signal.

4. The method of claim 1, executing a synchronization process to set at least one of a transmit drive point on the first node and a receive sample point on the second node.

5. The method of claim 1, executing a synchronization process to set at least one of a transmit drive point on the first node and a receive sample point on the second node, and including transmitting a control signal related to the synchronization process via a wired interconnect structure between the first and second node.

6. The method of claim 1, including producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting the timing of at least one of the transmit drive signal at the first node and the receive sample signal at the second node to coordinate communication between the first and second nodes.

7. The method of claim 1, including producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting the timing of at least one of the transmit drive signal at the first node and the receive sample signal at the second node in increments of 10 picoseconds or less to coordinate communication between the first and second nodes.

8. The method of claim 1, including producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting at least one of the transmit drive signal at the first node and the receive sample signal at the second node in increments of 1 picosecond or less to coordinate communication between the first and second nodes.

9. The method of claim 1, including generating the timing reference signal at one of the first and second nodes.

10. The method of claim 1, including producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting at least one of the transmit drive signal at the first node and the receive sample signal at the second node, wherein the adjusting includes:

producing a phase locked clock signal in response to the timing reference signal, providing a source for a plurality of phase shifted copies of the phase locked clock signal and selecting one of the plurality of phase shifted copies in response to a control parameter.

11. The method of claim 1, including producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting at least one of the transmit drive signal at the first node and the receive sample signal at the second node, wherein the adjusting includes:

producing a phase locked clock signal having a frequency greater than 1 GHz in response to the timing reference signal, providing a source for a plurality of phase shifted copies of the phase locked clock signal and selecting one of the plurality of phase shifted copies in response to a control parameter, where the plurality of phase shifted copies includes at least 50 phase shifted copies.

12. The method of claim 1, wherein the first and second nodes comprise circuits on first and second integrated circuits which are separated by a distance of less than 2 meters.

13. The method of claim 1, wherein the first and second nodes comprise circuits on first and second integrated circuits which are separated by a distance of less than one half of a meter.

14. The method of claim 1, including transmitting and receiving a plurality of radio signals carrying data in parallel between the first and second nodes in response to the timing reference signal.

15. The method of claim 1, wherein the wired interconnect structure comprises a power supply wire, and including delivering the timing reference signal via the power supply wire.

16. The method of claim 1, including:

transmitting another radio signal in response to the timing reference signal at the second node, the other radio signal carrying data; and

receiving the other radio signal in response to the timing reference signal at the first node.

17. A system comprising:

a first integrated circuit and a second integrated circuit;

a wired interconnect structure coupled to the first and second integrated circuits;

a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;

the first integrated circuit including

a data source;

a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure;

a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal;

a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; and

the second integrated circuit including

a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure;

a receive timing circuit which produces a receive timing signal in response to the timing reference signal;

a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal.

18. The system of claim 17, wherein the clock circuit comprises circuitry on one of the first integrated circuit and the second integrated circuit.

19. The system of claim 17, wherein the radio transmitter comprises a pulse position modulation circuit.

20. The system of claim 17, wherein the radio transmitter comprises an ultra-wide band radio transmitter.

21. The system of claim 17, including logic on the first integrated circuit which executes a synchronization process to set timing for at least one of the transmit timing signal for the radio transmitter and the receive timing signal for the radio receiver.

22. The system of claim 17, including logic on the first integrated circuit which executes a synchronization process to set timing for the transmit timing signal for the radio transmitter, the synchronization process including communication of a control signal related to the synchronization process via a wired interconnect structure with the second integrated circuit.

23. The system of claim 17, including logic on the second integrated circuit which executes a synchronization process to set timing for the receive timing signal for the radio receiver, the synchronization process including communication of a control signal related to the synchronization process via a wired interconnect structure with the first integrated circuit.

24. The system of claim 17, including circuitry on the first integrated circuit to adjust timing of the transmit timing signal to coordinate communication between the first and second integrated circuits.

25. The system of claim 17, including circuitry to adjust the timing of the transmit timing signal on the first integrated circuit by amounts of 10 picoseconds or less to coordinate communication between the first and second integrated circuits.

26. The system of claim 17, including circuitry to adjust the timing of the transmit timing signal on the first integrated circuit by amounts of 1 picosecond or less to coordinate communication between the first and second integrated circuits.

27. The system of claim 17, including circuitry on the second integrated circuit to adjust timing of the receive timing signal to coordinate communication between the first and second integrated circuits.

28. The system of claim 17, including circuitry to adjust the timing of the receive timing signal on the second integrated circuit by amounts of 10 picoseconds or less to coordinate communication between the first and second integrated circuits.

29. The system of claim 17, including circuitry to adjust the timing of the receive timing signal on the second integrated circuit by amounts of 1 picosecond or less to coordinate communication between the first and second integrated circuits.

30. The system of claim 17, including circuitry to adjust the timing of the transmit timing signal on the first integrated circuit, including

a phase locked loop which produces a phase locked clock signal in response to the timing reference signal,

a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, and

selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.

31. The system of claim 17, including circuitry to adjust the timing of the transmit timing signal on the first integrated circuit, including

a phase locked loop which produces a phase locked clock signal having a frequency of at least 1 GHz in response to the timing reference signal,

a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, the plurality of phase shifted copies including at least 50 phase shifted copies, and

selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.

32. The system of claim 17, including circuitry to adjust the timing of the receive timing signal on the second integrated circuit, including

a phase locked loop which produces a phase locked clock signal in response to the timing reference signal,

a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, and

selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.

33. The system of claim 17, including circuitry to adjust the timing of the receive timing signal on the second integrated circuit, including

a phase locked loop which produces a phase locked clock signal having a frequency of at least 1 GHz in response to the timing reference signal,

a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, the plurality of phase shifted copies including at least 50 phase shifted copies, and

selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.

34. The system of claim 17, wherein the first and second integrated circuits are mounted on a support structure and separated by a distance of less than 2 meters.

35. The system of claim 17, wherein the system includes a circuit board, and the first and second integrated circuits are mounted on the circuit board and separated by a distance of less than one half of a meter.

36. The system of claim 17, wherein the wired interconnect structure includes a power supply wire, and the clock circuit transmits the timing reference signal via the power supply wire.

37. The system of claim 17, including:

a radio receiver on the first integrated circuit; and

a radio transmitter on the second integrated circuit.

38. A system comprising:

a first integrated circuit and a second integrated circuit mounted on a support structure and separated by a distance of less than 10 meters;

a wired interconnect structure coupled to the first and second integrated circuits;

a clock circuit coupled to the wired interconnect structure transmitting a timing reference signal on the wired interconnect structure;

the first integrated circuit including

a data source;

a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure;

a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal, including circuitry to adjust the timing of the transmit timing signal by amounts of 10 picoseconds or less to synchronize communication between the first and second integrated circuits;

logic coupled with the transmit timing circuit which executes a synchronization process to set the timing for the transmit timing signal for the radio transmitter, the synchronization process including communication of a control signal related to the synchronization process via the wired interconnect structure with the second integrated circuit.

a radio transmitter coupled to the transmit timing circuit and the data source which transmits an ultra-wide band impulse radio signal carrying data from the data source in response to the transmit timing signal; and

the second integrated circuit including

a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure;

a receive timing circuit which produces a transmit timing signal in response to the timing reference signal;

a radio receiver coupled to the receive timing circuit which receives the ultra-wide band impulse radio signal carrying data from the data source in response to the receive timing signal.