Method and system for establishing an adaptable offset for a receiver

• US 20050276352A1
• Filed: 06/15/2005
• Published: 12/15/2005
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: Robert Bosch Corporation (Robert Bosch GmbH), Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Pacsai, Ernest Edmond
• Granted Patent: US 7,864,889 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A method and system of establishing an offset for a receiver. In one embodiment, a method includes receiving an input signal and generating a first signal. The method can further include integrating the input signal and the first signal at a reference node. In addition, the method can include comparing the input signal to a signal at the reference node and generating an output signal, analyzing the output signal to determine whether the output signal contains noise, and modifying the first signal based on the analysis of the output signal.

Claims

1. A method of establishing an offset for a receiver, the method comprising:

receiving an input signal;

generating a first signal;

integrating the input signal and the first signal at a reference node;

comparing the input signal to a signal at the reference node and generating an output signal;

analyzing the output signal to determine whether the output signal contains noise; and

modifying the first signal based on the analysis of the output signal.

2. The method as claimed in claim 1, further comprising coupling a capacitor to the reference node.

3. The method as claimed in claim 1, further comprising filtering the input signal.

4. The method as claimed in claim 1, further comprising regulating the first signal with a resistor.

5. The method as claimed in claim 1, wherein modifying the first signal includes modifying a pulse width of the first signal.

6. The method as claimed in claim 1, wherein modifying the first signal includes modifying a frequency of the first signal.

7. The method as claimed in claim 1, wherein modifying the first signal includes modifying an amplitude of the first signal.

8. The method as claimed in claim 1, wherein comparing the input signal to a signal at the reference node includes comparing an amplitude of the input signal to an amplitude of the signal at the reference node.

9. The method as claimed in claim 8, wherein comparing the input signal to a signal at the reference node and generating an output signal includes generating an output signal that includes the input signal if the amplitude of the input signal is greater than the amplitude of the signal at the reference node and generating an output signal that includes the signal at the reference node if the amplitude of the signal at the reference node is greater than the amplitude of the input signal.

10. The method as claimed in claim 8, wherein comparing the input signal to a signal at the reference node and generating an output signal includes generating an output signal that includes a logic high output signal if the amplitude of the input signal is greater than the amplitude of the signal at the reference node and generating an output signal that includes a logic low output signal if the amplitude of the signal at the reference node is greater than the amplitude of the input signal.

11. The method as claimed in claim 1, wherein analyzing the output signal to determine whether the output signal contains noise includes determining if the output signal conforms to a format.

12. The method as claimed in claim 1, wherein modifying the first signal based on the analysis of the output signal includes increasing a pulse width of the first signal if the output signal contains noise.

13. The method as claimed in claim 1, wherein modifying the first signal based on the analysis of the output signal includes decreasing a pulse width of the first signal if the output signal does not contain noise.

14. A receiver with an adjustable offset, the receiver comprising:

a comparator having a first input coupled to a first node, a reference input coupled to a reference node, and an output, the comparator configured to compare an input signal at the first input to a signal at the reference node, and to generate an output signal; and

a processor having an input coupled to the output of the comparator and an output coupled to the reference node, the processor configured to generate a first signal, to receive the output signal of the comparator on the input, to analyze the output signal of the comparator to determine whether the output signal of the comparator contains information that conforms to a predetermined format, and to modify the first signal based on the analysis of the output signal of the comparator.

15. The receiver as claimed in claim 14, further comprising a capacitor coupled to the reference input.

16. The receiver as claimed in claim 14, further comprising a reference resistor coupled between the input node and the reference node.

17. The receiver as claimed in claim 14, further comprising a regulating resistor coupled to the second output of the processor.

18. The receiver as claimed in claim 14, wherein the output signal includes the input signal if the amplitude of the input signal is greater than the amplitude of the signal at the reference node and the output signal includes the signal at the reference node if the amplitude of the signal at the reference node is greater than the amplitude of the input signal.

19. The receiver as claimed in claim 14, wherein the output signal includes a logic high output signal if the amplitude of the input signal is greater than the amplitude of the signal at the reference node and the output signal includes a logic low output signal if the amplitude of the signal at the reference node is greater than the amplitude of the input signal.

20. The receiver as claimed in claim 14, wherein the processor is configured to increase a pulse width of the first signal if the output signal does not contain information that conforms to a predetermined format.

21. The receiver as claimed in claim 20, wherein the processor is configured to determine if a pulse width of the first signal is a maximum width.

22. The receiver as claimed in claim 21, wherein the processor is configured to delay a predetermined amount of time if the pulse width of the first signal is the maximum width.

23. The receiver as claimed in claim 14, wherein the processor is configured to decrease a pulse width of the first signal if the output signal contains information that conforms to a predetermined format.

24. The receiver as claimed in claim 22, wherein the processor is configured to determine if a pulse width of the first signal is a minimum width.

25. The receiver as claimed in claim 23, wherein the processor is configured to delay a predetermined amount of time if the pulse width of the first signal is the minimum width.

26. A receiver comprising:

means for receiving an input signal;

means for generating a first signal;

means for comparing a version of the input signal and a version of the first signal;

means for generating a result signal;

means for analyzing the result signal to determine whether the result signal contains information that conforms to a predetermined information format; and

means for modifying the first signal based on analyzing the result signal.

27. The receiver as claimed in claim 26, further comprising means for regulating the first signal.