Logic components from organic field effect transistors

• US 20050277240A1
• Filed: 03/14/2003
• Published: 12/15/2005
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Fix, Walter, Ullmann, Andreas, Ficker, Jurgen
• Granted Patent: US 7,223,995 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 19/10 comprising field-effect transistors

Abstract

The invention makes it possible, for the first time, to produce, despite conventional p-type MOS technology, fast logical gates based on organic field effect transistors. This is primarily due to the early saturation effect of OFETs having very thin semi-conducting layers, and, furthermore, to the use of OFETs having specific properties as the organic logic components and to a novel layout of the circuit containing these logic components.

Claims

1. A logic gate, comprising at least one first and one second organic field effect transistor (OFET), each OFET transistor including a semi-conductor layer, of which transistors said first OFET is a p-type OFET and said second OFET can serve in the logic gate as a resistor, and as a result of specific treatment of the organic semi-conductor layer of said second OFET, said second OFET without a gate potential has OFF currents that are only approximately one order of magnitude lower than the ON currents so that said second OFET can still be switched off by an applied positive gate potential.

2. A logic gate as defined in claim 1, in which said first OFET has a semi-conducting layer having a thickness of from about 5 to about 30 nm.

3. A logic gate as defined in claim 1, in which said first and second OFETs each have a semi-conducting layer having a thickness of from about 5 to about 30 nm.

5. A logic gate as defined in claim 1 which comprises at least four of said OFETs.

7. A logic gate as defined in claim 2 which comprises at least four of said OFETs.

8. A logic gate as defined in claim 3 which comprises at least four of said OFETs.

9. A logic gate as defined in any one of the previous claims having two data lines (input and output), which have different potentials.

10. A logic gate as defined in claim 1, in which said first OFET has a semi-conducting layer having a negative threshold voltage.

11. A logic gate as defined in claim 1, in which said first and second OFETs each have a semi-conducting layer having a negative threshold voltage.

4. (canceled)

6. (canceled)