METHODS FOR FORMING SEMICONDUCTOR STRUCTURES

• US 20050277249A1
• Filed: 05/26/2004
• Published: 12/15/2005
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,098,105 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a first material and a second material over the substrate, the first and second materials being selectively etchable relative to one another, the first material being formed to be a lattice and the second material being formed to be repeating regions spaced from one another by segments of the lattice, the repeating regions forming an array, the array having a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;

the second pitch being about twice as big as the first pitch;

replacing at least some of the first material of the lattice with one or more conductive materials of a gateline; and

replacing at least some of the second material with doped semiconductor material to form elevationally-elongated source/drain regions over the substrate.

2. The method of claim 1 wherein the replacing at least some of the first material occurs before the replacing at least some of the second material.

3. The method of claim 1 wherein the replacing at least some of the second material occurs before the replacing at least some of the first material.

4. The method of claim 1 wherein the first material comprises silicon nitride and the second material comprises silicon dioxide.

5. The method of claim 1 wherein the first material consists essentially of silicon nitride and the second material consists essentially of silicon dioxide.

6. The method of claim 1 wherein the first material comprises silicon dioxide and the second material comprises silicon nitride.

7. The method of claim 1 wherein the first material consists essentially of silicon dioxide and the second material consists essentially of silicon nitride.

8. The method of claim 1 wherein the one or more conductive materials of the gateline include conductively-doped silicon.

9. The method of claim 1 wherein the one or more conductive materials of the gateline include one or more metals.

10. The method of claim 1 wherein the one or more conductive materials of the gateline include one or more metal alloys.

11. The method of claim 1 wherein the substrate comprises monocrystalline semiconductor material and wherein at least some of the doped semiconductor material of the elevationally-elongated source/drain regions is epitaxially grown from the monocrystalline semiconductor material of the substrate.

12. The method of claim 1 wherein:

the substrate comprises monocrystalline semiconductor material;

some of the doped semiconductor material of the elevationally-elongated source/drain regions is single crystal material epitaxially grown from the monocrystalline semiconductor material of the substrate; and

some of the doped semiconductor material of the elevationally-elongated source/drain regions is not single crystal material.

13. The method of claim 1 further comprising forming a digit line over and in electrical connection with some of the elevationally-elongated source/drain regions.

14. The method of claim 13 wherein the digit line is over and in electrical connection with a first set of the elevationally-elongated source/drain regions, and is not in electrical connection with a second set of the source/drain regions;

and further comprising forming memory storage devices over and in electrical connection with the second set of source/drain regions.

15. The method of claim 14 wherein the memory storage devices are capacitors.

16. A method for forming a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a nitride-containing material lattice over the substrate;

the lattice defining an array of non-nitride regions spaced from one another by segments of the lattice;

replacing nitride-containing material of the lattice with one or more conductive materials of a gateline; and

replacing non-nitride regions with doped semiconductor material to form elevationally-elongated source/drain regions.

17. The method of claim 16 wherein the array has a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;

and wherein the second pitch is larger than the first pitch.

18. The method of claim 17 wherein the second pitch is about twice as big as the first pitch.

19. The method of claim 16 wherein only some of the lattice is replaced by the one or more conductive materials of the gateline;

and wherein some of the lattice is replaced by dielectric material provided between the gateline and the vertically-extending source/drain regions.

20. The method of claim 16 wherein the nitride-containing material comprises silicon nitride.

21. The method of claim 16 wherein the nitride-containing material consists essentially of silicon nitride.

22. The method of claim 16 wherein the nitride-containing material consists of silicon nitride.

23. The method of claim 16 wherein the non-nitride regions comprise silicon dioxide prior to replacing the non-nitride regions with the doped semiconductor material.

24. The method of claim 16 wherein the non-nitride regions consist essentially of silicon dioxide prior to replacing the non-nitride regions with the doped semiconductor material.

25. The method of claim 16 wherein the non-nitride regions consist of silicon dioxide prior to replacing the non-nitride regions with the doped semiconductor material.

26. The method of claim 16 wherein the doped semiconductor material comprises epitaxially-grown silicon.

27. The method of claim 16 wherein the doped semiconductor material consists essentially of doped epitaxially-grown silicon.

28. The method of claim 16 wherein the doped semiconductor material consists of doped epitaxially-grown silicon.

29. The method of claim 16 further comprising forming a digit line over and in electrical connection with some of the elevationally-elongated source/drain regions.

30. The method of claim 29 wherein the digit line is over and in electrical connection with a first set of the elevationally-elongated source/drain regions, and is not in electrical connection with a second set of the source/drain regions;

and further comprising forming memory storage devices over and in electrical connection with the second set of source/drain regions.

31. The method of claim 30 wherein the memory storage devices are capacitors.

32. A method for forming a semiconductor structure, comprising:

providing a first semiconductor material;

forming an oxide-containing material over the first semiconductor material;

forming openings extending through the oxide-containing material;

forming nitride-containing spacers within the openings to narrow the openings;

extending the narrowed openings into the first semiconductor material, the narrowed openings having a first portion extending within the first semiconductor material and a second portion over the first portion;

providing a dielectric material to fill the first portion of the openings and leave the second portion not filled;

providing a nitride-containing material over the dielectric material to fill the second portion of the openings;

replacing the oxide-containing material with a doped second semiconductor material to form elevationally-elongated source/drain regions; and

replacing the nitride-containing material and nitride-containing spacers with one or more conductive materials of a gateline.

33. The method of claim 32 wherein the nitride-containing material and nitride-containing spacers comprise the same composition as one another.

34. The method of claim 32 wherein the nitride-containing material and nitride-containing spacers comprise silicon nitride.

35. The method of claim 32 wherein the nitride-containing material and nitride-containing spacers consist essentially of silicon nitride.

36. The method of claim 32 wherein the nitride-containing material and nitride-containing spacers consist of silicon nitride.

37. The method of claim 32 wherein the dielectric material is a first dielectric material, and further comprising providing a second dielectric material between the elevationally-elongated source/drain regions and the gateline.

38. The method of claim 32 further comprising forming a digit line in electrical connection with some of the source/drain regions, and forming capacitor constructions in electrical connection with others of the source/drain regions.

39. The method of claim 38 wherein the digit line is formed to be elevationally above said some of the source/drain regions.

40. The method of claim 32 wherein the first semiconductor material is monocrystalline silicon, and wherein the second semiconductor material is silicon epitaxially grown from the first semiconductor material.

41. The method of claim 32 wherein the openings are trenches longitudinally elongated along a defined horizontal direction, wherein the nitride-containing material is a first nitride-containing material, and wherein the first ntride-containing material within the openings is in the form of strips extending longitudinally in the horizontal direction;

the method further comprising;

forming a second nitride-containing material in strips extending along a defined vertical direction;

the first and second nitride-containing materials together forming a lattice;

wherein the oxide-containing material is in the form of an array of pillars, individual pillars of the array being surrounded by the lattice of the first and second nitride-containing materials; and

replacing the second nitride-containing material with said one or more conductive materials simultaneously with the replacing of the first nitride-containing material.

42. The method of claim 41 wherein the first and second nitride-containing materials comprise the same composition as one another.

43. The method of claim 41 wherein the first and second nitride-containing materials comprise silicon nitride.

44. The method of claim 41 wherein the first and second nitride-containing materials consist essentially of silicon nitride.

45. The method of claim 41 wherein the first and second nitride-containing materials consist of silicon nitride.

46. A method for forming a semiconductor structure, comprising:

providing a first semiconductor material;

forming an oxide-containing material over the first semiconductor material;

forming a hard mask layer over the oxide-containing material;

patterning the hard mask layer into a plurality of spaced lines extending along a defined horizontal direction, the spaced lines being separated by first gaps;

forming nitride-containing spacers along the hard mask to narrow the first gaps;

extending the narrowed first gaps through the oxide-containing material;

removing the hard mask layer while leaving the nitride-containing spacers;

the spacers forming sets of paired lines extending along the narrowed first gaps;

filling the narrowed first gaps with a first nitride-containing material, the first nitride-containing material extending upwardly between the sets of paired lines to form nitride-containing pillars over the oxide-containing material, the first nitride-containing material and nitride-containing spacers together being incorporated into spaced horizontally-extending pillars over the oxide-containing material, the spaced horizontally-extending pillars being separated by second gaps;

extending the second gaps through the oxide-containing material; and

filling the second gaps with a second nitride-containing material.

47. The method of claim 46 wherein the oxide-containing material comprises silicon dioxide.

48. The method of claim 46 wherein:

the filling the narrowed first gaps with the first nitride-containing material comprises forming the first nitride-containing material over the nitride-containing spacers and across regions of the oxide between the nitride-containing spacers that are ultimately to be the second gaps; and

the incorporating the first nitride-containing material and nitride-containing spacers into the spaced horizontally-extending pillars comprises anisotropically etching the first nitride-containing material to remove the first nitride-containing material from across the regions and thereby form the second gaps.

49. The method of claim 46 wherein:

the first and second nitride-containing materials are the same as one another in composition;

the spaced lines and first gaps repeat along a vertical direction to define a first vertical pitch, the first vertical pitch having a first distance corresponding to a line/first gap pair;

the first nitride-containing material within the narrowed first gaps and the second nitride-containing material within the second gaps form horizontally-extending nitride-containing lines spaced from one another by lines of the oxide-containing material;

the lines of oxide-containing material and lines of nitride-containing material forming a repeating pattern along the vertical direction to define a second vertical pitch, the second vertical pitch having a second distance corresponding to a nitride-containing-material line/oxide-containing-material line pair; and

the second distance is about one-half of the first distance.

50. The method of claim 46 wherein the nitride-containing spacers, first nitride-containing material and second nitride-containing material all contain the same composition as one another and together are incorporated into a nitride-containing lattice, and further comprising forming a plurality of transistor constructions by:

replacing at least some of the nitride-containing lattice with one or more electrically-conductive gateline materials; and

replace at least some of the oxide-containing material with conductively-doped source/drain structures.

51. The method of claim 50 wherein the composition of the nitride-containing spacers, first nitride-containing material and second nitride-containing material comprises silicon nitride.

52. The method of claim 50 wherein the composition of the nitride-containing spacers, first nitride-containing material and second nitride-containing material consists essentially of silicon nitride.

53. The method of claim 50 wherein the composition of the nitride-containing spacers, first nitride-containing material and second nitride-containing material consists of silicon nitride.

54-102. -102. (canceled)