Non-volatile memory and method of manufacturing the same

• US 20050277253A1
• Filed: 08/18/2005
• Published: 12/15/2005
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Kato, Kiyoshi
• Granted Patent: US 7,550,334 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

Claims

1. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor island having tapered side edges on an insulating surface;

forming a first insulating film on the semiconductor island by thermal oxidation of the semiconductor island;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

2. A method for manufacturing a non-volatile memory according to claim 1, wherein the taper angle of the semiconductor island is 20 to 70°

.

3. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor layer on an insulating surface;

forming a photo resist mask having tapered side edges on the semiconductor layer;

etching the semiconductor layer to form a semiconductor island having tapered side edges by using the photo resist mask;

forming a first insulating film on the semiconductor island by thermal oxidation of the semiconductor island;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

4. A method for manufacturing a non-volatile memory according to claim 3, wherein the taper angle of the semiconductor island is 20 to 70°

.

5. A method for manufacturing a non-volatile memory according to claim 3, wherein the semiconductor layer is etched by anisotropic etching.

6. A method for manufacturing a non-volatile memory according to claim 5, wherein the selective ratio of the semiconductor and the resist is 0.2 through 2 during the anisotropic etching of the semiconductor.

7. A method for manufacturing a non-volatile memory according to claim 5, wherein the anisotropic etching is performed by using a mixture of CF₄ and O₂.

8. A method for manufacturing a non-volatile memory according to claim 5, wherein the anisotropic etching of the semiconductor is multi-stage etching having at least two stages.

9. A method for manufacturing a non-volatile memory according to claim 3, wherein the photo resist mask having tapered side edges is formed by fusing a surface of a photo resist through baking treatment.

10. A method for manufacturing a non-volatile memory according to claim 3, wherein the taper angle of the tapered resist is 20 to 70°

.

11. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor island having tapered side edges with two tiers on an insulating surface;

forming a first insulating film on the semiconductor island by thermal oxidation of the semiconductor island;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

12. A method for manufacturing a non-volatile memory according to claim 11, wherein the taper angle of the semiconductor island in the upper tier region is 20 to 50°

and the taper angle of the semiconductor island in the lower tier region is 40 to 70°

.

13. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor island having tapered side edges on an insulating surface;

forming a first insulating film on the semiconductor island by CVD;

thermally oxidizing a surface of the semiconductor island after the formation of the first insulating film;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

14. A method for manufacturing a non-volatile memory according to claim 13, wherein the taper angle of the semiconductor island is 20 to 70°

.

15. A method for manufacturing a non-volatile memory according to claim 13, wherein the first insulating film is formed by reduced pressure CVD.

16. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor layer on an insulating surface;

forming a photo resist mask having tapered side edges on the semiconductor layer;

etching the semiconductor layer to form a semiconductor island having tapered side edges by using the photo resist mask;

forming a first insulating film on the semiconductor island by CVD;

thermally oxidizing a surface of the semiconductor island after the formation of the first insulating film;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

17. A method for manufacturing a non-volatile memory according to claim 16, wherein the taper angle of the semiconductor island is 20 to 70°

.

18. A method for manufacturing a non-volatile memory according to claim 16, wherein the semiconductor layer is etched by anisotropic etching.

19. A method for manufacturing a non-volatile memory according to claim 18, wherein the selective ratio of the semiconductor and the resist is 0.2 through 2 during the anisotropic etching of the semiconductor.

20. A method for manufacturing a non-volatile memory according to claim 18, wherein the anisotropic etching is performed by using a mixture of CF₄ and O₂.

21. A method for manufacturing a non-volatile memory according to claim 18, wherein the anisotropic etching of the semiconductor is multi-stage etching having at least two stages.

22. A method for manufacturing a non-volatile memory according to claim 16, wherein the photo resist mask having tapered side edges is formed by fusing a surface of a photo resist through baking treatment.

23. A method for manufacturing a non-volatile memory according to claim 16, wherein the taper angle of the tapered resist is 20 to 70°

.

24. A method for manufacturing a non-volatile memory according to claim 16, wherein the first insulating film is formed by reduced pressure CVD.

25. A method for manufacturing a non-volatile memory, comprising:

forming a semiconductor island having tapered side edges with two tiers on an insulating surface;

forming a first insulating film on the semiconductor island by CVD;

thermally oxidizing a surface of the semiconductor island after the formation of the first insulating film;

forming a floating gate over the semiconductor island with the first insulating film interposed therebetween;

forming a second insulating film over the floating gate; and

forming a control gate over the floating gate with the second insulating film interposed therebetween.

26. A method for manufacturing a non-volatile memory according to claim 25, wherein the taper angle of the semiconductor island in the upper tier region is 20 to 50°

and the taper angle of the semiconductor island in the lower tier region is 40 to 70°

.

27. A method for manufacturing a non-volatile memory according to claim 25, wherein the first insulating film is formed by reduced pressure CVD.