RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN

• US 20050277271A1
• Filed: 06/09/2004
• Published: 12/15/2005
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Byeong Y., Bronner, Gary B., Divakaruni, Ramachandra, Beintner, Jochen
• Granted Patent: US 7,037,794 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Claims

1. A method of forming a strained Si/SGOI structure comprising the steps of:

providing a structure including a silicon germanium-on-insulator (SGOI) substrate, a strained Si layer atop the SGOI substrate, a gate dielectric atop the strained Si layer, a gate polySi atop the gate dielectric and a pad nitride atop the gate dielectric;

forming a first stack of said pad nitride, said gate polySi, said gate dielectric, said strained Si, and a relaxed SiGe layer of the SGOI substrate;

forming a trench oxide in regions adjacent to said first stack;

removing said pad nitride from said first stack to expose said gate polySi layer;

forming a material layer comprising a polySi layer, an insulator and a cap nitride on said exposed gate polySi layer and said trench oxide, said polySi layer is in contact with said gate polySi layer;

forming a second stack comprising said cap nitride, said insulator, said polySi layer, and said gate polySi layer, said second stack is located atop said gate dielectric; and

forming a raised source/drain region on said strained Si layer in regions adjacent to said second stack, wherein during said forming exposed sidewalls of the trench oxide are protected with a sacrificial nitride spacer.

2. The method of claim 1 wherein SGOI substrate is formed by a process comprising thermally growing a SiGe layer atop a silicon-on-insulator layer and then relaxing the SiGe layer by annealing/oxidation;

wafer bonding;

wafer bonding and oxygen ion implantation;

oxygen ion implantation into a SiGe wafer;

providing a Si-containing substrate having a hole-rich region and a Ge layer, converting the hole rich region into a porous region, and annealing so as to convert the porous region into a buried oxide, while simultaneously forming a relaxed SiGe layer atop the buried oxide;

or by thermal mixing.

3. The method of claim 1 wherein said providing said first stack includes lithography and etching.

4. The method of claim 1 wherein said trench oxide is deposited in said regions adjacent to said first stack, said deposited occurs in a single step or in multiple steps.

5. The method of claim 1 wherein prior to forming said material stack said pad nitride is removed from the structure.

6. The method of claim 1 wherein said forming said second stack comprises lithography and etching.

7. The method of claim 1 wherein said forming said raised source/drain region comprises selective epitaxial Si growth.

8. The method of claim 1 wherein said sacrificial nitride spacers are formed prior to forming said raised source/drain region by deposition and etching.

9. The method of claim 1 further comprising removing said sacrificial nitride spacers to form divot regions on said strained Si layer, filling said divot regions with a nitride fill material, and forming oxide spacers on exposed sidewalls of said second stack.

10. A strained Si/SGOI structure comprising:

an active device region comprising a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of said strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and

a raised trench oxide region surrounding said active device region.

11. The strained Si/SGOI structure of claim 10 wherein said relaxed SiGe layer is recessed as compared to the overlying strained Si layer.

12. The strained Si/SGOI structure of claim 11 wherein said recess is not filled with any material.

13. The strained Si/SGOI structure of claim 10 further comprising an oxide spacer abutting said stack.

14. The strained Si/SGOI structure of claim 10 wherein said raised source/drain region is separated from said stack and said raised trench oxide by nitride.

15. The strained Si/SGOI structure of claim 10 wherein said strained Si layer is in contact with said raised trench oxide region.

16. The strained Si/SGOI structure of claim 10 wherein said gate polySi includes two polySi layers.

17. The strained Si/SGOI structure of claim 10 wherein said gate dielectric is an oxide or an oxide containing nitrogen therein.

18. The strained Si/SGOI structure of claim 10 wherein said gate dielectric is a thermal SiO₂ layer.

19. The strained Si/SGOI structure of claim 10 wherein said relaxed SiGe layer is an upper layer of a SGOI substrate, which further includes an underlying insulating layer, said insulating layer having said raised trench oxide region located thereon.

20. The strained Si/SGOI structure of claim 10 wherein an oxide cap is present on said gate polySi.