Dual damascene process

• US 20050277277A1
• Filed: 07/29/2005
• Published: 12/15/2005
• Est. Priority Date: 10/13/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Lin, Chih-Cheng
• Granted Patent: US 7,364,836 B2
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: G03F 7/095 having more than one photosensitive layer G03F7/075 takes precedence
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks

Abstract

A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. A second photoresist layer is formed over via patterned and the first photoresist layer. A trench line pattern is formed in the second photoresist layer by exposing to radiation of a second sensitivity. The layers are then etched and the trench line and via hole openings are filled with metal.

Claims

1. A method of photoresist processing on a substrate over which is formed composite layers of insulation comprising a first layer of dielectric and a second layer of dielectric, the method comprising:

forming a first photoresist layer over said composite layers of insulation;

patterning a via hole pattern in said first photoresist layer by exposing to radiation of a first sensitivity;

forming a second photoresist layer over via patterned and said first photoresist layer;

patterning a trench line pattern in second photoresist layer by exposing to radiation of a second sensitivity;

etching said second layer of dielectric underlying first layer of photoresist using the via hole pattern layer;

etching said composite layer of insulation, thereby transferring said trench line pattern into said second layer of dielectric and transferring said via hole pattern into said first layer of dielectric; and

filling the trench line and via hole openings with metal.

2. The method of claim 1, wherein the first photoresist layer is not sensitive to deep Uw radiation and the second photoresist layer is sensitive to deep UV radiation.

3. The method of claim 1, wherein said composite layers of insulation are low dielectric constant dielectric material which are selected from the group consisting of SiOF_x, SiOC_x, SiOH_x, in a thickness from approximately 4000 to 1200 Angstroms for said first layer of dielectric and in a thickness from approximately 4000 to 8000 Angstroms for said second layer of dielectric.

4. The method of claim 1, wherein said composite layers of insulation include an intermediate etch stop layer of dielectric is selected from the group consisting of silicon nitride, Si_xN_y, in a thickness from approximately 200 to 500 Angstroms, and which can be used in tandem with another etch stop layer or without said etch stop layers.

5. The method of claim 1, further comprising a top insulating layer over the composite layers of insulation, the top dielectric layer includes silicon oxynitride, SiON, in a thickness from approximately 300 to 1000 Angstroms.

6. The method of claim 1, wherein said first photoresist layer is positive type photoresist selected from the group consisting of I-line positive results, in a thickness from approximately 6000 to 10000 Angstroms and is selectively sensitive to and exposed to ultraviolet light I-line radiation of wavelength 365 nm.

7. The method of claim 1, wherein said second photoresist layer is positive type photoresist selected from the group consisting of positive DUV, 248 nm photoresist, in a thickness from approximately 5000 to 10000 Angstroms and is selectively sensitive to and exposed to ultraviolet light deep-UV radiation of wavelength 248 nm.

8. The method of claim 1, wherein said etching is performed in a two-step etch, selective reactive ion etch, RIE, with the first step process chemistry, for etching SiON and SiN:

CHF₃, C₂F₆, N₂ O₂ Ar, between 500 to 1200 Watts power, producing etch removal rates of between 1000 to 5000 Angstroms per minute, next applying;

CO, C₄F₈, C₂F₆, Ar;

the second step of etching to removing any SiN in the via;

CF₄, Ar O₂, CH₃F, between from 200 to 300 Watts power, producing etch rates from 1000 to 2000 Angtroms per minute, this both the trench and via openings are formed in a dual damascene process.

9. The method of claim 1, wherein the dual damascene trench/via is lined with a diffusion barrier, filled with conducting metal and whereby the excess metal is removed by chemical mechanical polish.

10. The method of claim 1, wherein multilevel conducting layers are fabricated by repeating the process steps described in the method of claim 1.

11. A method of dual damascene patterning by use of two-layered photoresist process, having different wavelength sensitivities for each layer, comprising:

providing a substrate over which is formed composite layers of insulation wherein said composite layers comprise a first layer of dielectric separated from a second layer of dielectric by an intermediate etch stop layer of dielectric;

forming a first photoresist layer over said composite layers of insulation;

patterning a via hole pattern in said first photoresist layer composed by exposing to radiation of a first sensitivity and developing said first photoresist layer by using a via hole mask;

forming a second photoresist layer over said first photoresist layer;

patterning a trench line pattern in said second photoresist layer by exposing to radiation of a second sensitivity and developing said second photoresist layer by using a trench line mask;

etching, in two-step process, said second layer of dielectric underlying said first layer of photoresist and transferring said via hole pattern into said second layer of dielectric;

etching said intermediate etch stop layer of dielectric under said second layer of dielectric and transferring said via hole pattern in said layer of photoresist into said intermediate etch stop layer of dielectric;

etching said composite layer of insulation transferring said trench line pattern into said first layer of photoresist and into said second layer of dielectric to form a trench line opening, and at the same time transferring said via hole pattern- into said intermediate etch stop layer of dielectric and into said first layer of dielectric to form a via hole opening;

removing said layers of photoresist and any exposed insulating material in the trench line opening and via hole opening;

depositing metal into the trench line and via hole opening with subsequent removal of excess metal by chemical mechanical polishing back, to form inlaid conducting interconnects lines and contact vias, in a dual damascene process.

12. The method of claim 11, wherein said substrate is semiconductor single crystal silicon or an IC module.

13. The method of claim 11, wherein said composite layers of insulation are low dielectric constant dielectric material which are selected from the group consisting of SiOF_x, SiOC_x, SiOH_x, in a thickness from approximately 4000 to 1200 Angstroms for said first layer of dielectric and in a thickness from approximately 4000 to 8000 Angstroms for said second layer of dielectric.

14. The method of claim 11, wherein said intermediate etch stop layer of dielectric is selected from the group consisting of silicon nitride, Si_xN_y, in a thickness from approximately 200 to 500 Angstroms, and can be used in tandem with another etch stop layer.

15. The method of claim 11, wherein said second layer of dielectric is silicon oxynitride, SiON, in a thickness from approximately 300 to 1000 Angstroms.

16. The method of claim 11, wherein said first photoresist layer is positive type photoresist selected from the group consisting of I-line positive resists, in a thickness from approximately 6000 to 10000 Angstroms and is selectively sensitive to and exposed to ultraviolet light I-line radiation of wavelength 365 nm.

17. The method of claim 11, wherein said second photoresist layer is positive type photoresist selected from the group consisting of positive DUV, 248 nm photoresist, in a thickness from approximately 5000 to 10000 Angstroms and is selectively sensitive to and exposed to ultraviolet light deep-UV radiation of wavelength 248 nm.

18. The method of claim 11, wherein said etching is performed in a two-step etch, selective reactive ion etch, RIE, with the first step process chemistry, for etching SiON and SiN:

CHF₃, C₂F₆, N₂ O₂ Ar, between 500 to 1200 Watts power, producing etch removal rates of between 1000 to 5000 Angstroms per minute, next applying;

CO, C₄F₈, C₂F₆, Ar;

the second step of etching to removing any SiN in the via;

CF₄, Ar O₂, CH₃F, between from 200 to 300 Watts power, producing etch rates from 1000 to 2000 Angstroms per minute, thus both the trench and via openings are formed in a dual damascene process.

19. The method of claim 11, wherein the dual damascene trench/via is lined with a diffusion barrier, filled with conducting metal and whereby the excess metal is removed by chemical mechanical polish.

20. A method for patterning in a semiconductor wafer having a dielectric layer with a lower portion and an upper portion over the lower portion, the method comprising:

providing a first photoresist layer over the upper dielectric layer portion, the first photoresist layer sensitive to first radiation;

patterning and developing a via hole in the first photoresist layer using the first radiation;

providing a second photoresist layer over the patterned and developed first photoresist layer, the second photoresist layer filling the via hole and being sensitive to a second radiation;

patterning and developing the second photoresist layer to form a trench over the filled via hole, using the second radiation;

etching the upper and lower dielectric layer portions to form a trench pattern in the upper dielectric layer portion that corresponds to the trench pattern formed in the second photoresist layer and a via hole pattern in the lower dielectric layer portion that corresponds to the via hole in the first photoresist layer.