Semiconductor device with a high thermal dissipation efficiency

• US 20050277280A1
• Filed: 06/09/2005
• Published: 12/15/2005
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Vettiger, Peter, Despont, Michel, Lantz, Mark A., Michel, Bruno, Brunschwiler, Thomas J.
• Granted Patent: US 7,271,034 B2
• Time in Patent Office: Days
• US Class Current: 438/616
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/4875 Connection or disconnection of other leads to or from bases or plates
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Provides semiconductor devices and method for fabricating devices having a high thermal dissipation efficiency. An example device comprises a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of connected fins. A process for fabricating such a semiconductor device includes forming a thermally conducting structure on a carrier and attaching the thermally conducting structure formed on the carrier to a surface of the semiconductor device via soldering.

Claims

1. A method for fabricating a semiconductor device, the method comprising the steps of:

providing a carrier having a seed layer;

providing a patterned mask layer on the seed layer of the carrier, said patterned mask layer having a recess structure;

depositing a thermally conducting material on the patterned mask layer in the recess structure, thus forming structure elements of a thermally conducting structure;

depositing a solder on the thermally conducting structure;

removing the patterned mask layer and the seed layer between the structure elements of the thermally conducting structure;

attaching the thermally conducting structure to a surface of a semiconductor device via soldering.

2. A method as recited in claim 1, comprising the further step of planarizing the patterned mask layer and the thermally conducting structure after said step of depositing the thermally conducting material to achieve a planar surface of the patterned mask layer and the thermally conducting structure.

3. A method as recited in claim 1, comprising the further step of coating the surface of the semiconductor device with an adhesion layer prior to said step of attaching the thermally conducting structure to the surface of the semiconductor device.

4. A method as recited in claim 1, comprising the step of providing the carrier in form of a transparent substrate coated with a polyimide layer, said seed layer being formed on top of the polyimide layer.

5. A method as recited in claim 4, comprising the further steps of:

removing the carrier; and

attaching a manifold layer to the thermally conducting structure attached to the surface of the semiconductor device.

6. A method as recited in claim 4, comprising the further steps of:

removing the carrier; and

integrating the semiconductor device with the thermally conducting structure attached to the surface of the semiconductor device into a device for jet impingement cooling.

7. A method as recited in claim 1, wherein the semiconductor device comprises at least two semiconductor chips attached to a common substrate, and further comprising the step of attaching said thermally conducting structure to the surfaces of the at least two semiconductor chips.

15. A method as recited in claim 1, comprising the further steps of:

planarizing the patterned mask layer and the thermally conducting structure after said step of depositing the thermally conducting material to achieve a planar surface of the patterned mask layer and the thermally conducting structure;

coating the surface of the semiconductor device with an adhesion layer prior to said step of attaching the thermally conducting structure to the surface of the semiconductor device;

providing the carrier in form of a transparent substrate coated with a polyimide layer, said seed layer being formed on top of the polyimide layer; and

removing the carrier and attaching a manifold layer to the thermally conducting structure attached to the surface of the semiconductor device, wherein the semiconductor device comprises at least two semiconductor chips attached to a common substrate, and further comprising the step of attaching said thermally conducting structure to the surfaces of the at least two semiconductor chips.

17. A method as recited in claim 2, comprising the further step of coating the surface of the semiconductor device with an adhesion layer prior to said step of attaching the thermally conducting structure to the surface of the semiconductor device.

18. A method as recited in claim 3, comprising the step of providing the carrier in form of a transparent substrate coated with a polyimide layer, said seed layer being formed on top of the polyimide layer.

8. A semiconductor device comprising a thermally conducting structure attached to a surface of the semiconductor device via soldering, said thermally conducting structure being essentially formed of a thermally conducting material and comprising an array of freestanding fins, studs or frames, or a grid of connected fins.

9. A semiconductor device as recited in claim 8, further comprising an adhesion layer coating the surface of the semiconductor device, said thermally conducting structure being attached to the adhesion layer.

10. A semiconductor device as recited in claim 8, further comprising a manifold layer attached to the thermally conducting structure.

11. A semiconductor device as recited in claim 10, wherein said manifold layer is attached to the thermally conducting structure via spring elements.

12. A semiconductor device as recited in claim 8, further comprising at least two semiconductor chips attached to a common substrate, said thermally conducting structure being attached to the surfaces of the semiconductor chips.

13. A semiconductor device as recited in claim 12, wherein the manifold layer is attached to the thermally conducting structure of the semiconductor chips, said manifold layer comprising a thinning between the semiconductor chips.

14. A semiconductor device as recited in claim 8, wherein the semiconductor device is integrated into a device for jet impingement cooling.

19. A semiconductor device as recited in claim 9, further comprising a manifold layer attached to the thermally conducting structure.

20. A semiconductor device as recited in claim 9, wherein the semiconductor device is integrated into a device for jet impingement cooling.

16. A semiconductor device comprising:

a thermally conducting structure attached to a surface of the semiconductor device via soldering, said thermally conducting structure being essentially formed of a thermally conducting material and comprising an array of freestanding fins, studs or frames, or a grid of connected fins;

an adhesion layer coating the surface of the semiconductor device, said thermally conducting structure being attached to the adhesion layer;

a manifold layer attached to the thermally conducting structure, wherein said manifold layer is attached to the thermally conducting structure via spring elements; and

at least two semiconductor chips attached to a common substrate, said thermally conducting structure being attached to the surfaces of the semiconductor chips, wherein the manifold layer is attached to the thermally conducting structure of the semiconductor chips, said manifold layer comprising a thinning between the semiconductor chips.