Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
First Claim
1. A method for making a stackable semiconductor chip layer comprising:
- providing a semiconductor substrate having first surface and a second surface, defining electronic circuitry on said first surface in a series of semiconductor process steps, defining a trench having an interior surface on said first surface wherein said trench is defined concurrently with said electronic circuitry during and as part of said semiconductor process steps, disposing a dielectric material upon said interior surface, depositing an electrically conductive material upon said dielectric material, removing a predetermined portion of said second surface whereby said conductive material is exposed to form an electrically conductive via.
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Accused Products
Abstract
A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
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Citations
12 Claims
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1. A method for making a stackable semiconductor chip layer comprising:
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providing a semiconductor substrate having first surface and a second surface, defining electronic circuitry on said first surface in a series of semiconductor process steps, defining a trench having an interior surface on said first surface wherein said trench is defined concurrently with said electronic circuitry during and as part of said semiconductor process steps, disposing a dielectric material upon said interior surface, depositing an electrically conductive material upon said dielectric material, removing a predetermined portion of said second surface whereby said conductive material is exposed to form an electrically conductive via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for making a stackable semiconductor chip layer comprising:
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providing a semiconductor substrate having a thickness and having first surface and a second surface, defining electronic circuitry on said first surface in a series of semiconductor process steps to define one or more integrated circuit die, defining a trench having an interior surface on at least one of said integrated circuit die wherein said trench is defined concurrently with said electronic circuitry during and as part of said semiconductor process steps, disposing a dielectric material upon said interior surface of said trench, depositing an electrically conductive material upon said dielectric material and within said trench, defining a plurality of grooves into said first surface, said grooves penetrating into said first surface at a predetermined distance less than said thickness whereby said one or more integrated circuit dies remain integral with said substrate, mounting said substrate to a flat rigid plate to support said substrate, said first surface of said substrate being releasably mounted to said plate, removing a predetermined portion of said second surface whereby said thickness is reduced to expose said plurality of said grooves and to expose said electrically conductive material within said trench, said dies remaining mounted to said plate, releasing said one or more dies from said plate.
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Specification