Network interface device that can offload data transfer processing for a TCP connection from a host CPU

• US 20050278459A1
• Filed: 01/20/2005
• Published: 12/15/2005
• Est. Priority Date: 10/14/1997
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Starr, Daryl D., Blightman, Stephen E.J.
• Granted Patent: US 7,627,684 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: H04L 45/66 Layer 2 routing, e.g. in Ethernet based MAN's
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/36 by determining packet size, e.g. maximum transfer unit [MTU]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9052 with buffers of different sizes
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/10 : of different types
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/34 : involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 67/62 : Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 : Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04L 69/16 : Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 : Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 : involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 : In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 : IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 : Network security protocols

Abstract

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.

Claims

1. A network interface device for a host computer, the network interface device comprising:

an application specific integrated circuit (ASIC) to process a Transmission Control Protocol (TCP) connection, including hardware to update a plurality of variables having values that represent a state of the TCP connection for the host, the TCP connection being at least in part identified by an Internet Protocol (IP) address and TCP port of the host and an IP address and TCP port of a remote host; and

a mechanism to transfer the state of the TCP connection from the network interface device to the host computer, the mechanism including a data structure representing the state.

2. The network interface device of claim 1, wherein the ASIC includes a microprocessor.

3. The network interface device of claim 1, wherein the mechanism to transfer a data structure includes a direct memory access (DMA) engine.

4. The network interface device of claim 1, further comprising protocol processing hardware to parse a TCP header of a received packet.

5. The network interface device of claim 1, further comprising protocol processing hardware to checksum an IP header and a TCP header of a received packet.

6. The network interface device of claim 1, wherein the protocol processing mechanism includes means for comparing a TCP source port and TCP destination port of a received packet header with the TCP port of the host and the TCP port of the remote host.

7. The network interface device of claim 1, wherein the protocol processing mechanism is part of a network interface card (NIC) that is connected to the host.

8. The network interface device of claim 1, wherein the protocol processing mechanism is part of a communication processing device (CPD) that is integrated into the host.

9. A network interface device for a host computer, the network interface device comprising:

a microprocessor running instructions to maintain a Transmission Control Protocol (TCP) connection including a plurality of variables having values that represent a state of the TCP connection for the host, the TCP connection being at least in part identified by an Internet Protocol (IP) address and TCP port of the host and an IP address and TCP port of a remote host; and

a mechanism controlled by the microprocessor to transfer the state of the TCP connection from the network interface device to the host computer.

10. The network interface device of claim 9, wherein the microprocessor is part of an application specific integrated circuit (ASIC).

11. The network interface device of claim 9, wherein the mechanism includes a direct memory access (DMA) engine.

12. The network interface device of claim 9, wherein the microprocessor is part of a network interface card (NIC) that is connected to the host.

13. The network interface device of claim 9, wherein the microprocessor is part of a communication processing device (CPD) that is integrated into the host.

14. The network interface device of claim 9, wherein the microprocessor includes a plurality of processors.

15. The network interface device of claim 9, further comprising protocol processing hardware to validate an IP header and a TCP header of a received packet.

16. The network interface device of claim 9, further comprising protocol processing hardware to parse an IP header and a TCP header of a received packet.

17. A network interface device for a host computer, the network interface device comprising:

a microprocessor; and

a computer-readable medium storing code that is executable on the microprocessor to maintain a Transmission Control Protocol (TCP) connection including a plurality of variables having values that represent a state of the TCP connection for the host, the TCP connection being at least in part identified by an Internet Protocol (IP) address and TCP port of the host and an IP address and TCP port of a remote host, the code including at least one instruction to transfer a data structure including the state of the TCP connection from the network interface device to the host computer.

18. The network interface device of claim 17, wherein the microprocessor is part of an application specific integrated circuit (ASIC).

19. The network interface device of claim 17, wherein the computer-readable medium is a memory that stores the TCP connection.

20. The network interface device of claim 17, wherein the microprocessor is part of a network interface card (NIC) that is connected to the host.

21. The network interface device of claim 17, wherein the microprocessor is part of a communication processing device (CPD) that is integrated into the host.

22. The network interface device of claim 17, further comprising protocol processing hardware to checksum an IP header and a TCP header of a packet.

23. The network interface device of claim 17, further comprising protocol processing hardware to parse an IP header and a TCP header of a packet.

24. The network interface device of claim 17, further comprising a direct memory access (DMA) engine that is controlled by the microprocessor to transfer the state to the host computer.