Apparatus and method to decrease boot time and hibernate awaken time of a computer system

• US 20050278522A1
• Filed: 08/16/2005
• Published: 12/15/2005
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Fortin, Michael R., Ergan, Cenk
• Granted Patent: US 7,203,830 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 2003/0697 device management, e.g. handlers, drivers, I/O schedulers
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

A method and apparatus to decrease the boot time and the hibernate awaken time of a computer system is presented. Static and dynamic configuration data is stored in flash memory. The size of flash memory is selected so that the initialization time of the configuration data stored in the flash memory is approximately equal to the spin-up time of the disk drive where the operating system is stored. During power down or entry into a hibernate mode, the computer system determines the static and dynamic configuration data to be stored in flash memory based on a history of prior uses. Data is also stored in the flash memory during system operation to reduce the number of times the disk drive is spun up. When the computer system is powered up or awakened from hibernation, the configuration data in flash memory is initialized while the disk drive is spinning up.

Claims

1. A computing apparatus comprising:

a display unit that is capable of generating video images;

an input device;

a non-persistent system memory;

a persistent storage device comprising;

at least one disk assembly for storing data including an operating system and programs having data files, the at least one disk assembly having a disk spin-up time;

a controller in communication with the at least one disk assembly, the controller having a cache buffer for caching data from the at least one disk assembly; and

a flash memory for storing static configuration data and dynamic configuration data, the flash memory in communication with the controller and having a size sufficient to store the static configuration data and the dynamic configuration data such that a time of loading the static configuration data and the dynamic configuration data into the non-persistent system memory is approximately equal to the disk spin-up time; and

a processor operatively coupled to the display unit, the input device, the non-persistent memory and the persistent storage device, wherein the processor is programmed to execute an operating system program.

2. The computing apparatus of claim 1, wherein one of the controller and processor directs the flash memory to buffer temporary operating system files while the processor is operating and further wherein the controller transfers the temporary files to the at least one disk assembly when one of powering down the computer apparatus, hibernating the computer apparatus, and detecting that available flash memory is below a threshold level.

3. The computing apparatus of claim 1, wherein the controller is programmed to indicate to the processor the existence of the flash memory.

4. The computing apparatus of claim 1, wherein the flash memory appears to the processor as at least one sector of the at least one disk assembly, and wherein the processor is programmed to determine the existence of the flash memory based on an access time of the at least one disk assembly.

5. The computing apparatus of claim 1, wherein the flash memory is backed-up by a battery.

6. The computing apparatus of claim 1, wherein the flash memory is the cache buffer.

7. The computing apparatus of claim 1, wherein the processor is programmed determine if the data stored in the flash memory is consistent with data stored in the at least one disk assembly.

8. The computing apparatus of claim 7, wherein the processor is programmed to bypass the flash memory if an inconsistency is detected between the data stored in the flash memory and the data stored in the at least one disk assembly.

9. The computing apparatus of claim 7, wherein determining if the data stored in the flash memory is consistent with data stored in the at least one disk assembly comprises determining whether there is a mismatch in one of a data partition and file system metadata.

10. The computing apparatus of claim 1, wherein the size of the flash memory is sufficient to buffer at least one write to the flash memory from at least one computer application during power down.

11. The computing apparatus of claim 1, wherein the controller is directed to create a state of the at least one write such that the at least one write can be moved to at least one sector in the disk after a subsequent one of the boot of a computer system and the resumption of a computer system from hibernation occurs.

12. The computing apparatus of claim 1, wherein the at least one write is readable from the flash memory by the processor if a read arrives for the at least one write and if the at least one write is still stored in the flash memory.

13. The computing apparatus of claim 1, wherein the non-persistent system memory is random access memory.

14. The computing apparatus of claim 1, wherein one of the controller and the processor determines a spin-up time of the at least disk assembly.