Warp processor for dynamic hardware/software partitioning

• US 20050278714A1
• Filed: 05/28/2004
• Published: 12/15/2005
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Lysecky, Roman Lev, Stitt, Gregory Michael, Vahid, Frank
• Granted Patent: US 7,356,672 B2
• Time in Patent Office: Days
• US Class Current: 717/159
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 8/53 Decompilation; Disassembly

Abstract

A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the binary to detect its critical code regions, and the dynamic partitioning module partitions the binary into critical and non-critical code regions, re-implements the critical code regions in the configurable logic, and then transforms the binary so that it accesses the configurable logic rather than execute the critical code regions.

Claims

1. A method for hardware/software partitioning, comprising:

(a) executing an application'"'"'s binary in a processor having configurable logic associated therewith;

(b) monitoring the executing binary to identify relative execution frequencies of the binary'"'"'s code regions in order to identify one or more critical and non-critical code regions in the binary;

(c) dynamically partitioning the binary between the critical and non-critical code regions;

(d) re-implementing the critical code regions in the configurable logic; and

(e) updating the binary to access the configurable logic rather than the critical code regions when the binary is executed in the processor.

2. The method of claim 1, wherein the dynamic partitioning step comprises:

decompiling the binary into a high-level representation;

analyzing the high-level representation to identify which of the critical code regions should be implemented in the configurable logic; and

compiling the identified critical code regions to create a configuration for the configurable logic.

3. The method of claim 2, wherein the decompiling step comprises loop rerolling, wherein loops that were unrolled by a compiler are identified and then rerolled into a generalized loop body.

4. The method of claim 2, wherein the compiling step comprises

performing a register-transfer (RT) synthesis to convert the identified critical code regions into a Boolean logic network;

performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network;

mapping the directed acyclic graph to create combinational logic block (CLB) nodes;

placing the combinational logic block nodes onto the configurable logic;

routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

5. The method of claim 2, wherein the warp processor performs Just-in-Time (JIT) compilation for any of a plurality of different configurable logic devices.

6. An apparatus for hardware/software partitioning, comprising:

(a) a processor having configurable logic associated therewith, wherein an application'"'"'s binary is executed in the processor;

(b) a profiler for monitoring the executing binary to identify relative execution frequencies of the binary'"'"'s code regions in order to identify one or more critical and non-critical code regions in the binary; and

(c) a dynamically partitioning module for dynamically partitioning the binary between the critical and non-critical code regions, for re-implementing the critical code regions in the configurable logic, and for updating the binary to access the configurable logic rather than the critical code regions when the binary is executed in the processor.

7. The apparatus of claim 6, wherein the dynamic partitioning module decompiles the binary into a high-level representation, analyzes the high-level representation to identify which of the critical code regions should be implemented in the configurable logic, and compiles the identified critical code regions to create a configuration for the configurable logic.

8. The apparatus of claim 7, wherein the decompilation comprises loop rerolling, wherein loops that were unrolled by a compiler are identified and then rerolled into a generalized loop body.

9. The apparatus of claim 7, wherein the dynamic partitioning module compiles the identified critical code regions by performing a register-transfer (RT) synthesis to convert the identified critical code regions into a Boolean logic network, performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network, mapping the directed acyclic graph to create combinational logic block (CLB) nodes, placing the combinational logic block nodes onto the configurable logic, and routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

10. The apparatus of claim 7, wherein the warp processor performs Just-in-Time (JIT) compilation for any of a plurality of different configurable logic devices.

11. An apparatus for hardware/software partitioning, comprising:

(a) means for executing an application'"'"'s binary in a processor having configurable logic associated therewith;

(b) means for monitoring the executing binary to identify relative execution frequencies of the binary'"'"'s code regions in order to identify one or more critical and non-critical code regions in the binary;

(c) means for dynamically partitioning the binary between the critical and non-critical code regions;

(d) means for re-implementing the critical code regions in the configurable logic; and

(e) means for updating the binary to access the configurable logic rather than the critical code regions when the binary is executed in the processor.

12. The apparatus of claim 11, wherein the means for dynamically partitioning comprises:

means for decompiling the binary into a high-level representation;

means for analyzing the high-level representation to identify which of the critical code regions should be implemented in the configurable logic; and

means for compiling the identified critical code regions to create a configuration for the configurable logic.

13. The apparatus of claim 12, wherein the means for decompiling comprises means for loop rerolling, wherein loops that were unrolled by a compiler are identified and then rerolled into a generalized loop body.

14. The apparatus of claim 12, wherein the means for compiling comprises:

means for performing a register-transfer (RT) synthesis to convert the identified critical code regions into a Boolean logic network;

means for performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network;

means for mapping the directed acyclic graph to create combinational logic block (CLB) nodes;

means for placing the combinational logic block nodes onto the configurable logic; and

means for routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

15. The apparatus of claim 12, wherein the warp processor performs Just-in-Time (JIT) compilation for any of a plurality of different configurable logic devices.

16. A method for implementing a configuration in configurable logic, comprising:

decompiling an application'"'"'s binary into a high-level representation;

analyzing the high-level representation to identify which code regions of the application'"'"'s binary should be implemented in the configurable logic;

compiling the identified code regions to create a configuration for the configurable logic, wherein the compiling step comprises;

performing a register-transfer (RT) synthesis to convert the identified code regions into a Boolean logic network;

performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network;

mapping the directed acyclic graph to create combinational logic block (CLB) nodes;

placing the combinational logic block nodes onto the configurable logic; and

routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

17. The method of claim 16, wherein the identified code regions comprise all the code regions of the application'"'"'s binary.

18. The method of claim 16, wherein the identified code regions comprise only a portion of the code regions of the application'"'"'s binary.

19. An apparatus for implementing a configuration in configurable logic, comprising:

(a) a processor;

(b) logic, performed by the processor, for decompiling an application'"'"'s binary into a high-level representation;

(c) logic, performed by the processor, for analyzing the high-level representation to identify which code regions of the application'"'"'s binary should be implemented in the configurable logic;

(d) logic, performed by the processor, for compiling the identified code regions to create a configuration for the configurable logic, wherein the logic for compiling comprises;

logic for performing a register-transfer (RT) synthesis to convert the identified code regions into a Boolean logic network;

logic for performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network;

logic for mapping the directed acyclic graph to create combinational logic block (CLB) nodes;

logic for placing the combinational logic block nodes onto the configurable logic; and

logic for routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

20. The apparatus of claim 19, wherein the identified code regions comprise all the code regions of the application'"'"'s binary.

21. The apparatus of claim 19, wherein the identified code regions comprise only a portion of the code regions of the application'"'"'s binary.

22. An apparatus for implementing a configuration in configurable logic, comprising:

means for decompiling an application'"'"'s binary into a high-level representation;

means for analyzing the high-level representation to identify which code regions of the application'"'"'s binary should be implemented in the configurable logic;

means for compiling the identified code regions to create a configuration for the configurable logic, wherein the means for compiling comprises;

means for performing a register-transfer (RT) synthesis to convert the identified code regions into a Boolean logic network;

means for performing a logic synthesis to create a directed acyclic graph (DAG) of the Boolean logic network;

means for mapping the directed acyclic graph to create combinational logic block (CLB) nodes;

means for placing the combinational logic block nodes onto the configurable logic; and

means for routing between inputs, outputs, and combinational logic block nodes within the configurable logic in order to generate the configuration for the configurable logic.

23. The apparatus of claim 22, wherein the identified code regions comprise all the code regions of the application'"'"'s binary.

24. The apparatus of claim 22, wherein the identified code regions comprise only a portion of the code regions of the application'"'"'s binary.