Semiconductor device

• US 20050280029A1
• Filed: 08/16/2005
• Published: 12/22/2005
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Hideki, Nakamura, Katsumi, Kusunoki, Shigeru
• Granted Patent: US 7,115,944 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n⁻ silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n⁻ silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n⁻ silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n⁻ silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n⁻ silicon substrate (1).

Claims

1-17. -17. (canceled)

18. A semiconductor device, characterized by comprising:

a semiconductor substrate having a first main surface and a second main surface which are opposed to each other;

first and second insulating gate type field effect transistor portions respectively having source regions and drain regions, which are opposed to each other sandwiching channel formation regions, and gate electrodes which are opposed to said channel formation regions sandwiching gate insulating films;

a first stabilizing plate, made of a conductor or of a semiconductor, which is opposed to said drain region of said first insulating gate type field effect transistor portion sandwiching a first insulating film for a plate and that forms, together with said drain region of said first insulating gate type field effect transistor portion, a capacitor; and

a second stabilizing plate, made of a conductor or of a semiconductor, which is opposed to said drain region of said second insulating gate type field effect transistor portion sandwiching a second insulating film for a plate and that forms, together with said drain region of said second insulating gate type field effect transistor portion, a capacitor,

wherein said first insulating gate type field effect transistor portion is formed on said first main surface while said second insulating gate type field effect transistor portion is formed in said second main surface and a current is allowed to flow between said first and second insulating gate type field effect transistor portions.

19. The semiconductor device according to claim 18, characterized in that

a first stabilizing plate capacitor formed between said first stabilizing plate and said drain region of said first insulating gate type field effect transistor portion has a capacitance greater than that of a first gate-drain capacitor formed between said gate electrode and said drain region of said first insulating gate type field effect transistor portion, and

a second stabilizing plate capacitor formed between said second stabilizing plate and said drain region of said second insulating gate type field effect transistor portion has a capacitance greater than that of a second gate-drain capacitor formed between said gate electrode and said drain region of said second insulating gate type field effect transistor portion.

20. The semiconductor device according to claim 18, characterized in that

a plurality of transistors of the same type as said first insulating gate type field effect transistor is arranged side by side and two or more plates of the same type as said first stabilizing plate are arranged in a region sandwiched between two of said first insulating gate type field effect transistors,

a plurality of transistors of the same type as said second insulating gate type field effect transistor is arranged side by side and two or more plates of the same type as said second stabilizing plate are arranged in a region sandwiched between two of said second insulating gate type field effect transistors and in that the impurity concentration of a region in said drain region sandwiched between said two or more first stabilizing plates and the impurity concentration of a region in said drain region sandwiched between said two or more second stabilizing plates are higher than the impurity concentration of the other regions in said drain region.

21. The semiconductor device according to claim 18, characterized in that

said semiconductor substrate has a first trench for a gate created in said first main surface and a second trench for a gate created in said second main surface,

said gate electrode of said first insulating gate type field effect transistor portion fills in said first trench for a gate and

said gate electrode of said second insulating gate type field effect transistor portion fills in said second trench for a gate.

22. The semiconductor device according to claim 21, characterized in that

said gate electrode of said first insulating gate type field effect transistor portion has two sides opposed to each other and is opposed to said channel formation region of said first insulating gate type field effect transistor portion in each of said two sides and said gate electrode of said second insulating gate type field effect transistor portion has two sides opposed to each other and is opposed to said channel formation region of said second insulating gate type field effect transistor portion in each of said two sides.

23. The semiconductor device according to claim 18, characterized in that a plurality of cells each of which includes said first and second insulating gate type field effect transistor portions are arranged side by side and said first and second stabilizing plate are arranged in a terminal portion of said arranged plurality of cells.

24-26. -26. (canceled)