RE-CONFIGURABLE LOGIC ELEMENTS USING HEAT ASSISTED MAGNETIC TUNNELING ELEMENTS

• US 20050280058A1
• Filed: 06/16/2004
• Published: 12/22/2005
• Est. Priority Date: 06/16/2004
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Huai, Yiming, Pakala, Mahendra
• Granted Patent: US 7,098,494 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H03K 19/168 using thin-film devices
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A magnetic logic cell includes a magnetic element having a pinned layer, a free layer, and a spacer layer. The pinned and free layers have pinned and free layer magnetizations. The spacer layer resides between the pinned and free layers. In one aspect, the magnetic logic cell includes a first configuration line that is electrically connected to the magnetic element and carries a first current and a second configuration line electrically that is insulated from the magnetic element and the first configuration line and carries a second current. The first or second current alone cannot switch the free layer magnetization. The first and second currents together can switch the free layer magnetization. When the first current is driven through the magnetic element and the second current is provided, the combination sets the pinned layer magnetization direction. In one aspect, the pinned layer magnetization is set by heating the AFM layer to approximately at or above the blocking temperature. In order to configure the logic cell, an initial direction for the free layer magnetization is also set.

Claims

1. A magnetic logic cell comprising;

a magnetic element including a pinned layer, a free layer, and a spacer layer, the pinned layer having a pinned layer magnetization;

the free layer having a free layer magnetization, the spacer layer residing between the pinned layer and the free layer;

a first configuration line electrically connected to the magnetic element, the first configuration line for carrying a first current;

a second configuration line electrically insulated from the magnetic element and from the first configuration line, the second configuration line for carrying a second current, the first current and the second current alone incapable of switching the free layer magnetization, the first current and the second current together in a particular direction capable of switching the free layer magnetization, and wherein the first current driven through the magnetic element and the second current capable of setting the pinned layer magnetization to a pinned layer magnetization direction.

2. The logic cell of claim 1 wherein the magnetic element further includes;

an antiferromagnetic layer adjacent to the pinned layer, the antiferromagnetic layer having a blocking temperature such that the first current driven through the magnetic element is capable of heating the antiferromagnetic layer to at least the blocking temperature.

3. The logic cell of claim 2 wherein the antiferromagnetic layer includes IrMn.

4. The logic cell of claim 2 wherein the antiferromagnetic layer has a blocking temperature of between one hundred and two hundred degrees Celsius.

5. The logic cell of claim 2 further comprising:

a transistor coupled to the magnetic element such that the first current is driven through the magnetic element when the transistor is in a first set.

6. The logic cell of claim 2 wherein the logic cell performs an AND operation, wherein the pinned layer magnetization direction is antiparallel to an initial direction of the free layer magnetization, and wherein the pinned layer magnetization direction is a positive direction.

7. The logic cell of claim 2 wherein the logic cell performs an OR operation, and wherein the pinned layer magnetization direction is parallel to the initial direction of the free layer and wherein the pinned layer magnetization direction is a positive direction.

8. The logic cell of claim 2 wherein the logic cell performs an NOR operation, and wherein the pinned layer magnetization direction is antiparallel to the initial direction of the free layer and wherein the pinned layer magnetization direction is a negative direction.

9. The logic cell of claim 2 wherein the logic cell performs an NAND operation, and wherein the pinned layer magnetization direction is parallel to the initial direction of the free layer and wherein the pinned layer magnetization direction is a negative direction.

10. The logic cell of claim 2 wherein the spacer layer is a current confined layer.

11. The logic cell of claim 10 wherein the magnetic element is a ballistic magnetoresistive element.

12. The logic cell of claim 2 wherein the spacer layer is a tunneling barrier.

13. A magnetic logic array comprising:

a plurality of magnetic logic cells, each of the plurality of magnetic logic cells including a magnetic element having a pinned layer, a free layer, and a spacer layer, the pinned layer having a pinned layer magnetization;

the free layer having a free layer magnetization, the spacer layer residing between the pinned layer and the free layer;

a plurality of first configuration lines, each of the plurality of first configuration lines electrically connected to the magnetic element of a first portion of the plurality of magnetic logic cells, the first configuration line for carrying a first current having a first current magnitude;

a plurality of second configuration lines, each of the plurality of second configuration lines electrically insulated from the magnetic element and from the first configuration line of a second portion of the plurality of magnetic logic cells, the second configuration line for carrying a second current having a second current magnitude, the first current and the second current alone incapable of switching the free layer magnetization, the first current and the second current together in a particular direction capable of switching the free layer magnetization, and wherein the first current driven through the magnetic element and the second current capable of setting the pinned layer magnetization to a pinned layer magnetization direction.

14. The magnetic logic array of claim 13 wherein a first configuration line of the plurality of first configuration lines corresponds to a corresponding second configuration line of the plurality of second configuration lines, the first configuration line and the corresponding second configuration line being parallel only when directly aligned with a magnetic logic cell of the plurality of magnetic logic cells.

15. The magnetic logic array of claim 13 wherein each of the plurality of magnetic logic cells is separately selectable.

16. A method for configuring a magnetic logic cell for a particular operation, the magnetic logic cell including a magnetic element having a pinned layer, a free layer, and a spacer layer, the pinned layer having a pinned layer magnetization;

the free layer having a free layer magnetization, the spacer layer residing between the pinned layer and the free layer, and comprising;

setting pinned layer magnetization direction by driving a first current from through the magnetic element and driving a second current in proximity to the magnetic element that generates a magnetic field to set the pinned layer magnetization to a pinned layer magnetization direction;

setting an initial direction for the free layer magnetization by driving the first current and the second current in a particular direction.

17. The method of claim 16 wherein the magnetic element further includes an antiferromagnetic layer adjacent to the pinned layer, the antiferromagnetic layer having a blocking temperature such that the first current driven through the magnetic element is capable of heating the antiferromagnetic layer to at least the blocking temperature.

18. The method of claim 17 wherein the logic cell performs an AND operation, wherein the pinned layer magnetization direction setting step sets the pinned layer to a positive direction by driving the second current such that a magnetic field is provided in the positive direction at the pinned layer and wherein the initial direction setting step sets the free layer magnetization antiparallel to the pinned layer magnetization direction.

19. The method of claim 17 wherein the logic cell performs an OR operation, wherein the pinned layer magnetization direction setting step sets the pinned layer to a positive direction by driving the second current such that a magnetic field is provided in the positive direction at the pinned layer and wherein the initial direction setting step sets the free layer magnetization direction parallel to the pinned layer magnetization direction.

20. The method of claim 17 wherein the logic cell performs an NOR operation, wherein the pinned layer magnetization direction setting step sets the pinned layer to a negative direction by driving the second current such that a magnetic field is provided in the negative direction at the pinned layer and wherein the initial direction setting step sets the free layer magnetization direction antiparallel to the pinned layer magnetization direction.

21. The method of claim 17 wherein the logic cell performs an NAND operation, wherein the pinned layer magnetization direction setting step sets the pinned layer to a negative direction by driving the second current such that a magnetic field is provided in the negative direction at the pinned layer and wherein the initial direction setting step sets the free layer magnetization direction parallel to the pinned layer magnetization direction.

22. A magnetic logic cell comprising;

a pinned layer having a pinned layer magnetization;

a free layer having a free layer magnetization;

a spacer layer residing between the pinned layer and the free layer; and

an antiferromagnetic layer having a blocking temperature such that a first current driven through the magnetic element heats the antiferromagnetic layer to be in a sufficiently disordered state that the pinned layer magnetization can be set in a pinned layer magnetization direction;

wherein the first current alone is insufficient to switch the free layer magnetization.

23. The magnetic logic cell of claim 22 wherein a second configuration line electrically insulated from the magnetic element carries a second current alone incapable of switching the free layer magnetization, the first current and the second current together in a particular direction capable of switching the free layer magnetization, and wherein the first current driven through the magnetic element and the second current capable of setting the pinned layer magnetization to a pinned layer magnetization direction.

24. The magnetic logic cell of claim 22 wherein the first current heats the antiferromagnetic layer to at or above the blocking temperature.