Vertical memory device structures

• US 20050280061A1
• Filed: 09/03/2004
• Published: 12/22/2005
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,378,702 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01056 Barium [Ba]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/315 : with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Vertically oriented semiconductor memory cells are added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor memory cells are physically separated from each other, and are not disposed within the same semiconductor body. The plurality of vertically oriented semiconductor memory cells can be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures, which are then supplied with various dielectric coatings, gate electrodes, and contacts by means of further processing operations. Alternatively, the plurality of vertically oriented semiconductor memory cells may be completely fabricated prior to attachment. DRAMs, SRAMs, non-volatile memories, and combinations of memory types can be provided.

Claims

1. A semiconductor memory structure, comprising:

a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate; and

a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor memory cells disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor memory cells separated from each other by dielectric material;

wherein the stackable add-on layer is bonded to a layer of the substrate that is the greatest distance from the substrate; and

wherein the memory cell is a DRAM having at least one transistor.

2. The semiconductor structure of claim 1, wherein the vertically oriented memory cell comprises a vertical transistor and a serially connected capacitor in a SOI pillar.

3. The semiconductor memory structure of claim 1, wherein the vertically oriented semiconductor memory cell comprises a vertical transistor in an SOI pillar and a capacitor connected in series therewith, the capacitor disposed external to the first stackable add-on layer.

4. The semiconductor memory structure of claim 1, wherein the vertically oriented semiconductor memory cell comprises a first capacitor, a first access transistor serially connected to the first capacitor, a second access transistor serial connected to the first access transistor, and a second capacitor serially connected to the second access device;

wherein the first capacitor, the first access transistor, the second access transistor, and the second capacitor are all formed in a single vertically oriented SOI pillar.

5. The semiconductor memory structure of claim 1, wherein the vertically oriented semiconductor memory cell comprises two vertically oriented, serially connected transistors formed on a SOI pillar, the serially connected transistors further connected to a capacitor disposed external to the stackable add-on layer.

6. The semiconductor memory structure of claim 1, wherein the vertically oriented semiconductor memory cell comprises two vertically and serially connected transistors and a shared serially connected capacitor in a SOI pillar.

7. The semiconductor memory structure of claim 1, wherein the vertically oriented semiconductor memory cell comprises:

a first diode;

a first access transistor connected in series to the first diode;

a second access transistor connected in series to the first access transistor;

a third access transistor connected in series to the second access transistor;

a fourth access transistor connected in series to the third access transistor; and

a second diode connected in series to the fourth access transistor;

wherein the first diode, the first, second, third, and fourth transistors, and the second diode are formed on the same SOI pillar.

8. A semiconductor memory structure, comprising:

a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate;

a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor memory cells disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor devices separated from each other by dielectric material; and

the stackable add-on layer to a layer of the substrate that is the greatest distance from the substrate;

wherein the stackable add-on layer is bonded to a layer of the substrate that is the greatest distance from the substrate; and

wherein the memory cell is an SRAM having at least one Negative Differential Resistance device.

9. The semiconductor memory structure of claim 8, wherein the vertically oriented semiconductor memory cell comprises a vertically oriented transistor and a vertically oriented NDR-type Thyristor serially connected to each other.

10. The semiconductor memory structure of claim 9, wherein the vertically oriented transistor is formed on an SOI pillar and the vertically NDR-type Thyristor is formed on an SOI pillar.

11. The semiconductor memory structure of claim 9, wherein the vertically oriented transistor and the vertically NDR-type Thyristor are formed on two separated SOI pillars.

13. The semiconductor memory structure of claim 8, wherein the vertically oriented transistor and the vertically NDR-type Thyristor are formed on the same SOI pillar.

14. A semiconductor memory structure, comprising:

a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate;

a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor memory cells disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor devices separated from each other by dielectric material; and

the stackable add-on layer to a layer of the substrate that is the greatest distance from the substrate;

wherein the stackable add-on layer is bonded to a layer of the substrate that is the greatest distance from the substrate; and

wherein the memory cell is a nonvolatile memory having at least one transistor.

15. The semiconductor memory structure of claim 14, wherein the vertically oriented semiconductor nonvolatile memory cell comprises a vertical transistor having a floating gate and a control gate on a SOI pillar.

16. The semiconductor memory structure of claim 14, wherein the vertically oriented semiconductor nonvolatile memory cell comprises a vertical transistor having a charge-trapping gate insulator and a gate on a SOI pillar.

17. The semiconductor memory structure of claim 14, wherein at least two nonvolatile memory cells are vertically and serially connected on a first SOI pillar.

18. The semiconductor memory structure of claim 17, wherein the at least two nonvolatile memory cells on the first SOI pillar are serially connected by an interconnect line disposed on a dielectric layer, to a nonvolatile memory cell on a second SOI pillar.