Method of fabricating a FinFET

• US 20050280090A1
• Filed: 08/26/2005
• Published: 12/22/2005
• Est. Priority Date: 11/05/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
• Inventors: Nowak, Edward J., Anderson, Brent A., Rankin, Jed H.
• Granted Patent: US 7,247,908 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming a protective layer on at least one sidewall of the fin; and (e) removing the protective layer from the at least one sidewall in a channel region of the fin. In a second embodiment, the protective layer is converted to a protective spacer.

Claims

1-21. -21. (canceled)

22. A FinFET device, comprising:

a dielectric layer on a top surface of a semiconductor substrate, said dielectric layer having a thin region and a thick region;

a silicon fin having sidewalls, said fin on a top surface of said thick region of said dielectric layer; and

a conformal protective layer over at least a lower portion of at least one of said sidewalls, said protective layer extending under said fin between a bottom surface of said fin and a top surface of said thin region of said dielectric layer.

23. The FinFET device of claim 22, wherein said fin includes a channel region and source/drain regions.

24. The FinFET device of claim 23, further including:

a gate dielectric in direct physical contact with said sidewalls of of said fin in said channel region of said fin; and

a conductive gate in direct physical contact with said gate dielectric.

25. The FinFET device of claim 22, wherein said protective layer comprises tetraethoxysilane oxide or silicon nitride.

26. The FinFET device of claim 22, wherein said protective layer is about 15 to 50 Å

thick.

27. The FinFET device of claim 22, wherein said fin has a height of about 500 to 2000 Å

and has a width of about 200 to 500 Å

.

28. The FinFET device of claim 22, wherein said silicon fin comprises mono-crystalline silicon.

29. The FinFET of claim 22, wherein said fin has a top surface and first and second opposing sidewalls and said gate dielectric is formed over said top surface and both said first and second sidewalls of said fin.

30. The FinFET of claim 29, wherein said conductive gate is formed on said gate dielectric over said top surface and both said first and second sidewalls of said fin.

31. The FinFET of claim 23, wherein said thin region of said dielectric layer does not extend under said source/drain regions.

32. The FinFET of claim 23, wherein said thick region of said dielectric layer extends under said under said source/drain regions.

33. The FinFET device of claim 22 wherein said gate dielectric extends under said fin between a bottom surface of said fin and a top surface of said thin region of said dielectric layer.

35. The FinFET device of claim 22, wherein said fin includes a channel region and source/drain regions.

36. The FinFET device of claim 35 further including:

a gate dielectric in direct physical contact with said sidewalls of said fin in said channel region of said fin; and

a conductive gate in direct physical contact with said gate dielectric.

37. The FinFET device of claim 35, wherein said protective layer comprises tetraethoxysilane oxide or silicon nitride.

38. The FinFET device of claim 35, wherein said protective layer is about 15 to 50 Å

thick, said fin has a height of about 500 to 2000 Å and

has a width of about 200 to 500 Å

.

39. The FinFET device of claim 35, wherein said silicon fin comprises mono-crystalline silicon.

40. The FinFET of claim 35, wherein said fin has a top surface and first and second opposing sidewalls and said gate dielectric is formed over said top surface and both said first and second sidewalls of said fin.

41. The FinFET of claim 35, wherein said pedestal does not extend under said source/drain regions.

34. A FinFET device, comprising:

a dielectric layer on a top surface of a semiconductor substrate;

a dielectric pedestal integral with said dielectric layer and extending above a top surface of said dielectric layer;

a silicon fin having sidewalls, said fin on a top surface pedestal; and

a conformal protective layer over at least a lower portion of at least one of said sidewalls, said protective layer extending under said fin.